intel/jarrell: Apply ROMCC workaround
Taken from intel/xe7501devkit, maybe it had same symptoms once. The call to ich5_watchdog_on() has side-effect of exploding the requirements for ROMCC internal arrays at compile-time. The hard-coded limit in question is MAX_RHS in util/romcc.c, the default of 127 comes from the rhs field defined with 7 bits. Before this patch intel/jarrell builds were using upto MAX_RHS=102, while other ROMCC boards built even with MAX_RHS=10. This workaround brings intel/jarrell to the same level. Change-Id: I162d801f81d9196403d88636eb9cb291c950ded0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5348 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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@ -102,4 +102,8 @@ static void main(unsigned long bist)
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dump_pci_device(PCI_DEV(0, 0x00, 0));
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dump_bar14(PCI_DEV(0, 0x00, 0));
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#endif
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/* NOTE: ROMCC dies with an internal compiler error if the
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* following line is removed.
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*/
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print_debug("SDRAM is up.\n");
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}
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