diff --git a/src/northbridge/via/vx800/ddr2init/DramInit.c b/src/northbridge/via/vx800/ddr2init/dram_init.c similarity index 100% rename from src/northbridge/via/vx800/ddr2init/DramInit.c rename to src/northbridge/via/vx800/ddr2init/dram_init.c diff --git a/src/northbridge/via/vx800/ddr2init/DramInit.h b/src/northbridge/via/vx800/ddr2init/dram_init.h similarity index 97% rename from src/northbridge/via/vx800/ddr2init/DramInit.h rename to src/northbridge/via/vx800/ddr2init/dram_init.h index 36234bc46b..e7f5e72d50 100644 --- a/src/northbridge/via/vx800/ddr2init/DramInit.h +++ b/src/northbridge/via/vx800/ddr2init/dram_init.h @@ -197,59 +197,59 @@ typedef struct _DRAM_SIZE_INFO { //detection.c /*Step1 detect DRAM type, Read SPD data,command rate*/ CB_STATUS DRAMDetect(DRAM_SYS_ATTR * DramAttr); -//FreqSetting.c +//freq_setting.c /*Step2 set Frequency, calculate CAL*/ void DRAMFreqSetting(DRAM_SYS_ATTR * DramAttr); -//TimingSetting.c +//timing_setting.c /*Step3 Set DRAM Timing*/ void DRAMTimingSetting(DRAM_SYS_ATTR * DramAttr); -//DRDY_BL.c +//drdy_bl.c /*Step4 DRDY*/ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr); -//DRDY_BL.c +//drdy_bl.c /*Step5 Burst Length*/ void DRAMBurstLength(DRAM_SYS_ATTR * DramAttr); -//DrivingSetting.c +//driving_setting.c /*Step6 DRAM Driving Adjustment*/ void DRAMDriving(DRAM_SYS_ATTR * DramAttr); -//ClkCtrl.c +//clk_ctrl.c /*Step7 duty cycle control*/ void DutyCycleCtrl(DRAM_SYS_ATTR * DramAttr); -//ClkCtrl.c +//clk_ctrl.c /*Step8 DRAM clock phase and delay control*/ void DRAMClkCtrl(DRAM_SYS_ATTR * DramAttr); -//DevInit.c +//dev_init.c /*Step9 set register before init DRAM device*/ void DRAMRegInitValue(DRAM_SYS_ATTR * DramAttr); -//DevInit.c +//dev_init.c /*Step10 DDR and DDR2 initialize process*/ void DRAMInitializeProc(DRAM_SYS_ATTR * DramAttr); -//DQSSearch.c +//dqs_search.c /*Step11 Search DQS and DQ output delay*/ void DRAMDQSOutputSearch(DRAM_SYS_ATTR * DramAttr); -//DQSSearch.c +//dqs_search.c /*Step12 Search DQS input delay*/ void DRAMDQSInputSearch(DRAM_SYS_ATTR * DramAttr); -//RankMap.c +//rank_map.c /*Step13 Interleav function in rankmap.c*/ void DRAMBankInterleave(DRAM_SYS_ATTR * DramAttr); -//RankMap.c +//rank_map.c /*Step14 Sizing*/ void DRAMSizingMATypeM(DRAM_SYS_ATTR * DramAttr); -//FinalSetting.c +//final_setting.c /*Step15 DDR fresh counter setting*/ void DRAMRefreshCounter(DRAM_SYS_ATTR * DramAttr); -//FinnalSetting.c +//final_setting.c /*Step16 Final register setting for improve performance*/ void DRAMRegFinalValue(DRAM_SYS_ATTR * DramAttr); diff --git a/src/northbridge/via/vx800/ddr2init/DramUtil.c b/src/northbridge/via/vx800/ddr2init/dram_util.c similarity index 100% rename from src/northbridge/via/vx800/ddr2init/DramUtil.c rename to src/northbridge/via/vx800/ddr2init/dram_util.c diff --git a/src/northbridge/via/vx800/ddr2init/DramUtil.h b/src/northbridge/via/vx800/ddr2init/dram_util.h similarity index 100% rename from src/northbridge/via/vx800/ddr2init/DramUtil.h rename to src/northbridge/via/vx800/ddr2init/dram_util.h diff --git a/src/northbridge/via/vx800/ddr2init/Translatorddr2init.c b/src/northbridge/via/vx800/ddr2init/translator_ddr2_init.c similarity index 100% rename from src/northbridge/via/vx800/ddr2init/Translatorddr2init.c rename to src/northbridge/via/vx800/ddr2init/translator_ddr2_init.c diff --git a/src/northbridge/via/vx800/ddr2init/vx800/ClkCtrl.c b/src/northbridge/via/vx800/ddr2init/vx800/clk_ctrl.c similarity index 100% rename from src/northbridge/via/vx800/ddr2init/vx800/ClkCtrl.c rename to src/northbridge/via/vx800/ddr2init/vx800/clk_ctrl.c diff --git a/src/northbridge/via/vx800/ddr2init/vx800/Detection.c b/src/northbridge/via/vx800/ddr2init/vx800/detection.c similarity index 100% rename from src/northbridge/via/vx800/ddr2init/vx800/Detection.c rename to src/northbridge/via/vx800/ddr2init/vx800/detection.c diff --git a/src/northbridge/via/vx800/ddr2init/vx800/DevInit.c b/src/northbridge/via/vx800/ddr2init/vx800/dev_init.c similarity index 99% rename from src/northbridge/via/vx800/ddr2init/vx800/DevInit.c rename to src/northbridge/via/vx800/ddr2init/vx800/dev_init.c index 6a6ab22dce..bb0232589d 100644 --- a/src/northbridge/via/vx800/ddr2init/vx800/DevInit.c +++ b/src/northbridge/via/vx800/ddr2init/vx800/dev_init.c @@ -396,7 +396,7 @@ void InitDDR2CHA(DRAM_SYS_ATTR * DramAttr) // Step 9,10. check ODT value for EMRS(1) command - // according to ODTLookUp_TBL in DrivingSetting.c if there is one dimm in MB's one channel , the DDR2's ODT is 150ohm + // according to ODTLookUp_TBL in driving_setting.c if there is one dimm in MB's one channel , the DDR2's ODT is 150ohm // if there is two dimm in MB's one channel, the DDR2's ODT is 75 ohm DimmNum = DramAttr->DimmNumChA; diff --git a/src/northbridge/via/vx800/ddr2init/vx800/DQSSearch.c b/src/northbridge/via/vx800/ddr2init/vx800/dqs_search.c similarity index 100% rename from src/northbridge/via/vx800/ddr2init/vx800/DQSSearch.c rename to src/northbridge/via/vx800/ddr2init/vx800/dqs_search.c diff --git a/src/northbridge/via/vx800/ddr2init/vx800/DRDY_BL.c b/src/northbridge/via/vx800/ddr2init/vx800/drdy_bl.c similarity index 100% rename from src/northbridge/via/vx800/ddr2init/vx800/DRDY_BL.c rename to src/northbridge/via/vx800/ddr2init/vx800/drdy_bl.c diff --git a/src/northbridge/via/vx800/ddr2init/vx800/DrivingSetting.c b/src/northbridge/via/vx800/ddr2init/vx800/driving_setting.c similarity index 100% rename from src/northbridge/via/vx800/ddr2init/vx800/DrivingSetting.c rename to src/northbridge/via/vx800/ddr2init/vx800/driving_setting.c diff --git a/src/northbridge/via/vx800/ddr2init/vx800/FinalSetting.c b/src/northbridge/via/vx800/ddr2init/vx800/final_setting.c similarity index 100% rename from src/northbridge/via/vx800/ddr2init/vx800/FinalSetting.c rename to src/northbridge/via/vx800/ddr2init/vx800/final_setting.c diff --git a/src/northbridge/via/vx800/ddr2init/vx800/FreqSetting.c b/src/northbridge/via/vx800/ddr2init/vx800/freq_setting.c similarity index 100% rename from src/northbridge/via/vx800/ddr2init/vx800/FreqSetting.c rename to src/northbridge/via/vx800/ddr2init/vx800/freq_setting.c diff --git a/src/northbridge/via/vx800/ddr2init/vx800/RankMap.c b/src/northbridge/via/vx800/ddr2init/vx800/rank_map.c similarity index 100% rename from src/northbridge/via/vx800/ddr2init/vx800/RankMap.c rename to src/northbridge/via/vx800/ddr2init/vx800/rank_map.c diff --git a/src/northbridge/via/vx800/ddr2init/vx800/TimingSetting.c b/src/northbridge/via/vx800/ddr2init/vx800/timing_setting.c similarity index 100% rename from src/northbridge/via/vx800/ddr2init/vx800/TimingSetting.c rename to src/northbridge/via/vx800/ddr2init/vx800/timing_setting.c diff --git a/src/northbridge/via/vx800/ddr2init/vx800/UMARamSetting.c b/src/northbridge/via/vx800/ddr2init/vx800/uma_ram_setting.c similarity index 100% rename from src/northbridge/via/vx800/ddr2init/vx800/UMARamSetting.c rename to src/northbridge/via/vx800/ddr2init/vx800/uma_ram_setting.c diff --git a/src/northbridge/via/vx800/DrivingClkPhaseData.h b/src/northbridge/via/vx800/driving_clk_phase_data.h similarity index 100% rename from src/northbridge/via/vx800/DrivingClkPhaseData.h rename to src/northbridge/via/vx800/driving_clk_phase_data.h diff --git a/src/northbridge/via/vx800/examples/cache_as_ram_auto.c b/src/northbridge/via/vx800/examples/cache_as_ram_auto.c index 55468514e9..8f53975f89 100644 --- a/src/northbridge/via/vx800/examples/cache_as_ram_auto.c +++ b/src/northbridge/via/vx800/examples/cache_as_ram_auto.c @@ -43,7 +43,7 @@ #endif #include "cpu/x86/lapic/boot_cpu.c" -#include "DrivingClkPhaseData.c" +#include "driving_clk_phase_data.c" #include "northbridge/via/vx800/raminit.h" #include "northbridge/via/vx800/raminit.c" @@ -423,7 +423,7 @@ g) Rx73h = 32h DRAMDRDYSetting(&DramAttr); - Data = 0x80; // this value is same with DevInit.c + Data = 0x80; // this value is same with dev_init.c pci_write_config8(PCI_DEV(0, 0, 4), 0xa3, Data); pci_write_config8(PCI_DEV(0, 17, 7), 0x60, rambits << 2); Data = pci_read_config8(MEMCTRL, 0x88); diff --git a/src/northbridge/via/vx800/examples/DrivingClkPhaseData.c b/src/northbridge/via/vx800/examples/driving_clk_phase_data.c similarity index 99% rename from src/northbridge/via/vx800/examples/DrivingClkPhaseData.c rename to src/northbridge/via/vx800/examples/driving_clk_phase_data.c index 4028f02aa5..a93c9a03c4 100644 --- a/src/northbridge/via/vx800/examples/DrivingClkPhaseData.c +++ b/src/northbridge/via/vx800/examples/driving_clk_phase_data.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #include "northbridge/via/vx800/DrivingClkPhaseData.h" + #include "northbridge/via/vx800/driving_clk_phase_data.h" // DQS Driving //Reg0xE0, 0xE1 diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index 3d855ec4b5..6552085135 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -38,7 +38,7 @@ static void memctrl_init(device_t dev) { /* - set VGA in UMARamSetting.c, not in this function. + set VGA in uma_ram_setting.c, not in this function. */ #if 0 pci_write_config8(dev, 0x85, 0x20); diff --git a/src/northbridge/via/vx800/raminit.c b/src/northbridge/via/vx800/raminit.c index 58aef2561e..cd8cf2f3f8 100644 --- a/src/northbridge/via/vx800/raminit.c +++ b/src/northbridge/via/vx800/raminit.c @@ -38,24 +38,24 @@ #define PRINT_DEBUG_MEM_HEX32(x) #define DUMPNORTH() #endif -#include "northbridge/via/vx800/ddr2init/Translatorddr2init.c" -#include "northbridge/via/vx800/ddr2init/DramInit.h" +#include "northbridge/via/vx800/ddr2init/translator_ddr2_init.c" +#include "northbridge/via/vx800/ddr2init/dram_init.h" #include "northbridge/via/vx800/vx800_early_smbus.c" #include "northbridge/via/vx800/vx800_early_serial.c" -#include "northbridge/via/vx800/ddr2init/DramUtil.h" -#include "northbridge/via/vx800/ddr2init/DramUtil.c" -#include "northbridge/via/vx800/ddr2init/vx800/Detection.c" -#include "northbridge/via/vx800/ddr2init/vx800/FreqSetting.c" -#include "northbridge/via/vx800/ddr2init/vx800/TimingSetting.c" -#include "northbridge/via/vx800/ddr2init/vx800/DRDY_BL.c" -#include "northbridge/via/vx800/ddr2init/vx800/DrivingSetting.c" -#include "northbridge/via/vx800/ddr2init/vx800/ClkCtrl.c" -#include "northbridge/via/vx800/ddr2init/vx800/DevInit.c" -#include "northbridge/via/vx800/ddr2init/vx800/RankMap.c" -#include "northbridge/via/vx800/ddr2init/vx800/DQSSearch.c" -#include "northbridge/via/vx800/ddr2init/vx800/FinalSetting.c" -#include "northbridge/via/vx800/ddr2init/vx800/UMARamSetting.c" -#include "northbridge/via/vx800/ddr2init/DramInit.c" +#include "northbridge/via/vx800/ddr2init/dram_util.h" +#include "northbridge/via/vx800/ddr2init/dram_util.c" +#include "northbridge/via/vx800/ddr2init/vx800/detection.c" +#include "northbridge/via/vx800/ddr2init/vx800/freq_setting.c" +#include "northbridge/via/vx800/ddr2init/vx800/timing_setting.c" +#include "northbridge/via/vx800/ddr2init/vx800/drdy_bl.c" +#include "northbridge/via/vx800/ddr2init/vx800/driving_setting.c" +#include "northbridge/via/vx800/ddr2init/vx800/clk_ctrl.c" +#include "northbridge/via/vx800/ddr2init/vx800/dev_init.c" +#include "northbridge/via/vx800/ddr2init/vx800/rank_map.c" +#include "northbridge/via/vx800/ddr2init/vx800/dqs_search.c" +#include "northbridge/via/vx800/ddr2init/vx800/final_setting.c" +#include "northbridge/via/vx800/ddr2init/vx800/uma_ram_setting.c" +#include "northbridge/via/vx800/ddr2init/dram_init.c" /* * Support one dimm with up to 2 ranks */