soc/intel/xeon_sp: Move DMICTL lock

On SKX FSP-M does not return if this is set too early.

Tested on OCP/Tiogapass, boots.

Change-Id: Ib8ef7bab36bfd4b62988768753d10b4d7b7d567f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48657
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/xeon_sp/cpx/chip.c

@@ -79,6 +79,7 @@ static void chip_init(void *data)
 	fsp_silicon_init(false);
 	override_hpet_ioapic_bdf();
 	pch_enable_ioapic();
+	pch_lock_dmictl();
 	setup_lapic();
 	p2sb_unhide();
 }

src/soc/intel/xeon_sp/include/soc/pch.h

@@ -10,5 +10,6 @@ void pch_disable_devfn(struct device *dev);
 #endif
 
 void override_hpet_ioapic_bdf(void);
+void pch_lock_dmictl(void);
 
 #endif /* _SOC_PCH_H_ */

src/soc/intel/xeon_sp/pch.c

@@ -40,9 +40,6 @@ static void soc_config_acpibase(void)
 	reg32 = (0x3f << 18) | ACPI_BASE_ADDRESS | 1;
 	pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32);
 	pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8);
-
-	reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
-	pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK);
 }
 
 void bootblock_pch_init(void)
@@ -69,3 +66,9 @@ void override_hpet_ioapic_bdf(void)
 	p2sb_set_ioapic_bdf(ioapic_bdf);
 	p2sb_set_hpet_bdf(hpet_bdf);
 }
+
+void pch_lock_dmictl(void)
+{
+	uint32_t reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
+	pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK);
+}

src/soc/intel/xeon_sp/skx/chip.c

@@ -45,6 +45,7 @@ static void soc_init(void *data)
 	printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
 	fsp_silicon_init(false);
 	override_hpet_ioapic_bdf();
+	pch_lock_dmictl();
 }
 
 static void soc_final(void *data)