From 8351243e4a99c7159ec3257db272b735efff218c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 5 Jun 2013 07:19:31 +0300 Subject: [PATCH] Fix i82801a/b/c/d IOAPIC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Setting IRQ delivery to FSB got lost in the rebase process for commit e6143531. I captured following error on dmesg and this patch fixes it for i82801dx. ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 ..MP-BIOS bug: 8254 timer not connected to IO-APIC ...trying to set up timer (IRQ0) through the 8259A ... ..... (found apic 0 pin 2) ... ....... failed. ...trying to set up timer as Virtual Wire IRQ... ..... works. Change-Id: I0768976cc6b0deab213ad9bd4771e0f278de634c Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/3371 Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/southbridge/intel/i82801ax/lpc.c | 6 ++++++ src/southbridge/intel/i82801bx/lpc.c | 6 ++++++ src/southbridge/intel/i82801cx/lpc.c | 6 ++++++ src/southbridge/intel/i82801dx/lpc.c | 6 ++++++ 4 files changed, 24 insertions(+) diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c index db03a5897c..212c95f270 100644 --- a/src/southbridge/intel/i82801ax/lpc.c +++ b/src/southbridge/intel/i82801ax/lpc.c @@ -104,6 +104,12 @@ static void i82801ax_enable_ioapic(struct device *dev) printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); set_ioapic_id(IO_APIC_ADDR, 0x02); + + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write(IO_APIC_ADDR, 0x03, 0x01); } static void i82801ax_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c index c5e976c136..13b15996dc 100644 --- a/src/southbridge/intel/i82801bx/lpc.c +++ b/src/southbridge/intel/i82801bx/lpc.c @@ -105,6 +105,12 @@ static void i82801bx_enable_ioapic(struct device *dev) printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); set_ioapic_id(IO_APIC_ADDR, 0x02); + + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write(IO_APIC_ADDR, 0x03, 0x01); } static void i82801bx_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c index 79998bc722..f9c0ece4fe 100644 --- a/src/southbridge/intel/i82801cx/lpc.c +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -42,6 +42,12 @@ static void i82801cx_enable_ioapic(struct device *dev) printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); set_ioapic_id(IO_APIC_ADDR, 0x02); + + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write(IO_APIC_ADDR, 0x03, 0x01); } // This is how interrupts are received from the Super I/O chip diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 69ec110d6e..cf4e132e3b 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -68,6 +68,12 @@ static void i82801dx_enable_ioapic(struct device *dev) printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); set_ioapic_id(IO_APIC_ADDR, 0x02); + + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write(IO_APIC_ADDR, 0x03, 0x01); } static void i82801dx_enable_serial_irqs(struct device *dev)