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first round name simplification. drop the <component>_ prefix. 

the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.

Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)

- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong

Signed-off-by: <stepan@coresystems.de>

Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
stepan 2010-12-08 05:42:47 +00:00 committed by Stefan Reinauer
parent 1bc5ccac51
commit 836ae29ee3
455 changed files with 503 additions and 510 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/advantech/pcm-5820/romstage.c
View File

@ -27,7 +27,7 @@
#include "northbridge/amd/gx1/raminit.c"
#include "cpu/x86/bist.h"
#include "superio/winbond/w83977f/w83977f_early_serial.c"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#include "southbridge/amd/cs5530/enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1)

4
src/mainboard/amd/db800/romstage.c
View File

@ -31,8 +31,8 @@
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

4
src/mainboard/amd/dbm690t/romstage.c
View File

@ -43,8 +43,8 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
#include "southbridge/amd/rs690/early_setup.c"
#include "southbridge/amd/sb600/early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
static void memreset(int controllers, const struct mem_controller *ctrl) { }

6
src/mainboard/amd/mahogany/romstage.c
View File

@ -43,9 +43,9 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
#include "southbridge/amd/rs780/early_setup.c"
#include "southbridge/amd/sb700/early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }

6
src/mainboard/amd/mahogany_fam10/romstage.c
View File

@ -47,8 +47,8 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "southbridge/amd/rs780/early_setup.c"
#include "southbridge/amd/sb700/early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
#include <spd.h>
@ -69,7 +69,7 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "southbridge/amd/sb700/early_setup.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{

4
src/mainboard/amd/norwich/romstage.c
View File

@ -31,8 +31,8 @@
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
static inline int spd_read_byte(unsigned int device, unsigned int address)
{

6
src/mainboard/amd/pistachio/romstage.c
View File

@ -38,9 +38,9 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
#include "southbridge/amd/rs690/early_setup.c"
#include "southbridge/amd/sb600/early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb600/early_setup.c! */
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }

4
src/mainboard/amd/rumba/romstage.c
View File

@ -10,8 +10,8 @@
#include <cpu/amd/gx2def.h>
#include <cpu/amd/geode_post_code.h>
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

4
src/mainboard/amd/serengeti_cheetah/romstage.c
View File

@ -13,7 +13,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "southbridge/amd/amd8111/early_smbus.c"
#include <reset.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
@ -26,7 +26,7 @@
#include <cpu/amd/mtrr.h>
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

4
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
View File

@ -35,7 +35,7 @@
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <cpu/amd/model_10xxx_rev.h>
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "southbridge/amd/amd8111/early_smbus.c"
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include <lib.h>
@ -48,7 +48,7 @@
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

5
src/mainboard/amd/tilapia_fam10/romstage.c
View File

@ -47,8 +47,8 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "southbridge/amd/rs780/early_setup.c"
#include "southbridge/amd/sb700/early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@ -68,7 +68,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

4
src/mainboard/arima/hdama/romstage.c
View File

@ -9,7 +9,7 @@
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "southbridge/amd/amd8111/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -21,7 +21,7 @@
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <spd.h>
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)

4
src/mainboard/artecgroup/dbe61/romstage.c
View File

@ -33,8 +33,8 @@
#include "southbridge/amd/cs5536/cs5536.h"
#include "spd_table.h"
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
static int spd_read_byte(unsigned device, unsigned address)
{

2
src/mainboard/asi/mb_5blgp/romstage.c
View File

@ -27,7 +27,7 @@
#include "northbridge/amd/gx1/raminit.c"
#include "cpu/x86/bist.h"
#include "superio/nsc/pc87351/pc87351_early_serial.c"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#include "southbridge/amd/cs5530/enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)

2
src/mainboard/asi/mb_5blmp/romstage.c
View File

@ -28,7 +28,7 @@
#include "northbridge/amd/gx1/raminit.c"
#include "superio/nsc/pc87351/pc87351_early_serial.c"
#include "cpu/x86/bist.h"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#include "southbridge/amd/cs5530/enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)

6
src/mainboard/asrock/939a785gmh/romstage.c
View File

@ -44,9 +44,9 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
#include "southbridge/amd/rs780/early_setup.c"
#include "southbridge/amd/sb700/early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
#define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)

6
src/mainboard/asus/a8n_e/romstage.c
View File

@ -38,7 +38,7 @@
#include <cpu/amd/model_fxx_rev.h>
#include <console/console.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
#include "southbridge/nvidia/ck804/early_smbus.h"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -60,8 +60,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
#include "southbridge/nvidia/ck804/ck804_early_setup.c"
#include "southbridge/nvidia/ck804/early_setup_ss.h"
#include "southbridge/nvidia/ck804/early_setup.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "northbridge/amd/amdk8/early_ht.c"

6
src/mainboard/asus/a8v-e_deluxe/romstage.c
View File

@ -41,8 +41,8 @@ unsigned int get_sbdn(unsigned bus);
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
#include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
#include "southbridge/via/vt8237r/early_smbus.c"
#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
@ -79,7 +79,7 @@ void soft_reset(void)
}
}
#include "southbridge/via/k8t890/k8t890_early_car.c"
#include "southbridge/via/k8t890/early_car.c"
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"

6
src/mainboard/asus/a8v-e_se/romstage.c
View File

@ -41,8 +41,8 @@ unsigned int get_sbdn(unsigned bus);
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
#include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
#include "southbridge/via/vt8237r/early_smbus.c"
#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
@ -79,7 +79,7 @@ void soft_reset(void)
}
}
#include "southbridge/via/k8t890/k8t890_early_car.c"
#include "southbridge/via/k8t890/early_car.c"
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"

4
src/mainboard/asus/m2v-mx_se/romstage.c
View File

@ -45,7 +45,7 @@ unsigned int get_sbdn(unsigned bus);
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
#include "southbridge/via/vt8237r/early_smbus.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
@ -62,7 +62,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#include "southbridge/via/k8t890/k8t890_early_car.c"
#include "southbridge/via/k8t890/early_car.c"
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"

4
src/mainboard/asus/m2v/romstage.c
View File

@ -45,7 +45,7 @@ unsigned int get_sbdn(unsigned bus);
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
#include "southbridge/via/vt8237r/early_smbus.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
@ -64,7 +64,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#include "southbridge/via/k8t890/k8t890_early_car.c"
#include "southbridge/via/k8t890/early_car.c"
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"

5
src/mainboard/asus/m4a78-em/romstage.c
View File

@ -47,8 +47,8 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "southbridge/amd/rs780/early_setup.c"
#include "southbridge/amd/sb700/early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@ -68,7 +68,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

5
src/mainboard/asus/m4a785-m/romstage.c
View File

@ -47,8 +47,8 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "southbridge/amd/rs780/early_setup.c"
#include "southbridge/amd/sb700/early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@ -68,7 +68,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

2
src/mainboard/axus/tc320/romstage.c
View File

@ -28,7 +28,7 @@
#include "northbridge/amd/gx1/raminit.c"
#include "superio/nsc/pc97317/pc97317_early_serial.c"
#include "cpu/x86/bist.h"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#include "southbridge/amd/cs5530/enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)

2
src/mainboard/bcom/winnet100/romstage.c
View File

@ -28,7 +28,7 @@
#include "northbridge/amd/gx1/raminit.c"
#include "superio/nsc/pc97317/pc97317_early_serial.c"
#include "cpu/x86/bist.h"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#include "southbridge/amd/cs5530/enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)

2
src/mainboard/bcom/winnetp680/romstage.c
View File

@ -33,7 +33,7 @@
#include "lib/delay.c"
#include <lib.h>
#include <spd.h>
#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
#include "southbridge/via/vt8237r/early_smbus.c"
#include "superio/winbond/w83697hf/w83697hf_early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)

4
src/mainboard/broadcom/blast/romstage.c
View File

@ -9,7 +9,7 @@
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
#include "southbridge/broadcom/bcm5785/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -20,7 +20,7 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
#include "southbridge/broadcom/bcm5785/early_setup.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)

2
src/mainboard/dell/s1850/romstage.c
View File

@ -6,7 +6,7 @@
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include <console/console.h>
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "southbridge/intel/i82801ex/early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
#include "superio/nsc/pc8374/pc8374_early_init.c"
#include "cpu/x86/lapic/boot_cpu.c"

2
src/mainboard/digitallogic/adl855pc/romstage.c
View File

@ -10,7 +10,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "southbridge/intel/i82801dx/i82801dx.h"
#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
#include "southbridge/intel/i82801dx/early_smbus.c"
#include "northbridge/intel/i855/raminit.h"
#include "northbridge/intel/i855/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"

4
src/mainboard/digitallogic/msm800sev/romstage.c
View File

@ -12,8 +12,8 @@
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

2
src/mainboard/eaglelion/5bcm/romstage.c
View File

@ -8,7 +8,7 @@
#include <console/console.h>
#include "superio/nsc/pc97317/pc97317_early_serial.c"
#include "cpu/x86/bist.h"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#include "southbridge/amd/cs5530/enable_rom.c"
#include "northbridge/amd/gx1/raminit.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)

2
src/mainboard/getac/p470/acpi_tables.c
View File

@ -33,7 +33,7 @@
extern unsigned char AmlCode[];
#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
#include "southbridge/intel/i82801gx/nvs.h"
static void acpi_create_gnvs(global_nvs_t *gnvs)
{

2
src/mainboard/getac/p470/mainboard_smi.c
View File

@ -24,7 +24,7 @@
#include <console/console.h>
#include <cpu/x86/smm.h>
#include "southbridge/intel/i82801gx/i82801gx.h"
#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
#include "southbridge/intel/i82801gx/nvs.h"
#include "northbridge/intel/i945/udelay.c"
#include "ec.c"

8
src/mainboard/gigabyte/ga_2761gxdk/romstage.c
View File

@ -39,8 +39,8 @@
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/sis/sis966/sis966.h"
#include "southbridge/sis/sis966/sis966_early_smbus.c"
#include "southbridge/sis/sis966/sis966_enable_rom.c"
#include "southbridge/sis/sis966/early_smbus.c"
#include "southbridge/sis/sis966/enable_rom.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -52,7 +52,7 @@
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/sis/sis966/sis966_early_ctrl.c"
#include "southbridge/sis/sis966/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
@ -86,7 +86,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
#include "southbridge/sis/sis966/sis966_early_setup_ss.h"
#include "southbridge/sis/sis966/early_setup_ss.h"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"

8
src/mainboard/gigabyte/m57sli/romstage.c
View File

@ -36,7 +36,7 @@
#include <usbdebug.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
#include "southbridge/nvidia/mcp55/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -48,7 +48,7 @@
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO)
@ -69,8 +69,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
#include "southbridge/nvidia/mcp55/early_setup_ss.h"
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include "northbridge/amd/amdk8/amdk8_f.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"

5
src/mainboard/gigabyte/ma785gmt/romstage.c
View File

@ -43,8 +43,8 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "southbridge/amd/rs780/early_setup.c"
#include "southbridge/amd/sb700/early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@ -64,7 +64,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

5
src/mainboard/gigabyte/ma78gm/romstage.c
View File

@ -47,8 +47,8 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "southbridge/amd/rs780/early_setup.c"
#include "southbridge/amd/sb700/early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@ -68,7 +68,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

4
src/mainboard/hp/dl145_g1/romstage.c
View File

@ -9,7 +9,7 @@
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "southbridge/amd/amd8111/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -20,7 +20,7 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

4
src/mainboard/hp/dl145_g3/romstage.c
View File

@ -40,7 +40,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
#include "southbridge/broadcom/bcm5785/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -53,7 +53,7 @@
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
#include "southbridge/broadcom/bcm5785/early_setup.c"
#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)

4
src/mainboard/hp/dl165_g6_fam10/romstage.c
View File

@ -39,7 +39,7 @@
#include "option_table.h"
#include <console/console.h>
#include <cpu/amd/model_10xxx_rev.h>
#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
#include "southbridge/broadcom/bcm5785/early_smbus.c"
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include <lib.h>
@ -55,7 +55,7 @@
#include "northbridge/amd/amdfam10/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
//#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
#include "southbridge/broadcom/bcm5785/early_setup.c"
#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)

2
src/mainboard/ibase/mb899/acpi_tables.c
View File

@ -35,7 +35,7 @@ extern const unsigned char AmlCode[];
unsigned long acpi_create_slic(unsigned long current);
#endif
#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
#include "southbridge/intel/i82801gx/nvs.h"
static void acpi_create_gnvs(global_nvs_t *gnvs)
{
memset((void *)gnvs, 0, sizeof(*gnvs));

2
src/mainboard/ibase/mb899/mainboard_smi.c
View File

@ -21,7 +21,7 @@
#include <arch/romcc_io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
#include "southbridge/intel/i82801gx/nvs.h"
/* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler

4
src/mainboard/ibm/e325/romstage.c
View File

@ -10,7 +10,7 @@
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "southbridge/amd/amd8111/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -22,7 +22,7 @@
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <spd.h>
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)

4
src/mainboard/ibm/e326/romstage.c
View File

@ -10,7 +10,7 @@
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "southbridge/amd/amd8111/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -21,7 +21,7 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)

2
src/mainboard/iei/juki-511p/romstage.c
View File

@ -26,7 +26,7 @@
#include <arch/hlt.h>
#include <console/console.h>
#include "superio/winbond/w83977f/w83977f_early_serial.c"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#include "southbridge/amd/cs5530/enable_rom.c"
#include "cpu/x86/bist.h"
#include "pc80/udelay_io.c"
#include "northbridge/amd/gx1/raminit.c"

5
src/mainboard/iei/kino-780am2-fam10/romstage.c
View File

@ -47,8 +47,8 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "southbridge/amd/rs780/early_setup.c"
#include "southbridge/amd/sb700/early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
#define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
@ -70,7 +70,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

2
src/mainboard/iei/nova4899r/romstage.c
View File

@ -26,7 +26,7 @@
#include <arch/hlt.h>
#include <console/console.h>
#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#include "southbridge/amd/cs5530/enable_rom.c"
#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)

4
src/mainboard/iei/pcisa-lx-800-r10/romstage.c
View File

@ -31,8 +31,8 @@
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

2
src/mainboard/intel/d945gclf/acpi_tables.c
View File

@ -66,7 +66,7 @@ typedef struct acpi_oemb {
} __attribute__((packed)) acpi_oemb_t;
#endif
#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
#include "southbridge/intel/i82801gx/nvs.h"
#if OLD_ACPI
static void acpi_create_oemb(acpi_oemb_t *oemb)

2
src/mainboard/intel/d945gclf/mainboard_smi.c
View File

@ -21,7 +21,7 @@
#include <arch/romcc_io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
#include "southbridge/intel/i82801gx/nvs.h"
/* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler

4
src/mainboard/intel/eagleheights/romstage.c
View File

@ -31,8 +31,8 @@
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/acpi.h>
#include "southbridge/intel/i3100/i3100_early_smbus.c"
#include "southbridge/intel/i3100/i3100_early_lpc.c"
#include "southbridge/intel/i3100/early_smbus.c"
#include "southbridge/intel/i3100/early_lpc.c"
#include "reset.c"
#include "superio/intel/i3100/i3100_early_serial.c"
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"

2
src/mainboard/intel/jarrell/romstage.c
View File

@ -6,7 +6,7 @@
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include <console/console.h>
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "southbridge/intel/i82801ex/early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
#include "superio/nsc/pc87427/pc87427.h"
#include "cpu/x86/lapic/boot_cpu.c"

4
src/mainboard/intel/mtarvon/romstage.c
View File

@ -27,8 +27,8 @@
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "southbridge/intel/i3100/i3100_early_smbus.c"
#include "southbridge/intel/i3100/i3100_early_lpc.c"
#include "southbridge/intel/i3100/early_smbus.c"
#include "southbridge/intel/i3100/early_lpc.c"
#include "northbridge/intel/i3100/raminit.h"
#include "superio/intel/i3100/i3100.h"
#include "cpu/x86/mtrr/earlymtrr.c"

4
src/mainboard/intel/truxton/romstage.c
View File

@ -28,8 +28,8 @@
#include <pc80/mc146818rtc.h>
#include "pc80/udelay_io.c"
#include <console/console.h>
#include "southbridge/intel/i3100/i3100_early_smbus.c"
#include "southbridge/intel/i3100/i3100_early_lpc.c"
#include "southbridge/intel/i3100/early_smbus.c"
#include "southbridge/intel/i3100/early_lpc.c"
#include "northbridge/intel/i3100/raminit_ep80579.h"
#include "superio/intel/i3100/i3100.h"
#include "cpu/x86/lapic/boot_cpu.c"

2
src/mainboard/intel/xe7501devkit/romstage.c
View File

@ -8,7 +8,7 @@
#include <stdlib.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "southbridge/intel/i82801cx/i82801cx_early_smbus.c"
#include "southbridge/intel/i82801cx/early_smbus.c"
#include "northbridge/intel/e7501/raminit.h"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/intel/e7501/debug.c"

4
src/mainboard/iwill/dk8_htx/romstage.c
View File

@ -13,7 +13,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "southbridge/amd/amd8111/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "cpu/x86/lapic/boot_cpu.c"
@ -24,7 +24,7 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

4
src/mainboard/iwill/dk8s2/romstage.c
View File

@ -13,7 +13,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "southbridge/amd/amd8111/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "cpu/x86/lapic/boot_cpu.c"
@ -24,7 +24,7 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

4
src/mainboard/iwill/dk8x/romstage.c
View File

@ -13,7 +13,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "southbridge/amd/amd8111/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "cpu/x86/lapic/boot_cpu.c"
@ -24,7 +24,7 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

2
src/mainboard/jetway/j7f24/romstage.c
View File

@ -31,7 +31,7 @@
#include "cpu/x86/bist.h"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
#include "southbridge/via/vt8237r/early_smbus.c"
#include "superio/fintek/f71805f/f71805f_early_serial.c"
#include <lib.h>
#include <spd.h>

5
src/mainboard/jetway/pa78vm5/romstage.c
View File

@ -48,8 +48,8 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "southbridge/amd/rs780/early_setup.c"
#include "southbridge/amd/sb700/early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
#if CONFIG_TTYS0_BASE == 0x2f8
@ -75,7 +75,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

2
src/mainboard/kontron/986lcd-m/acpi_tables.c
View File

@ -35,7 +35,7 @@ extern const unsigned char AmlCode[];
unsigned long acpi_create_slic(unsigned long current);
#endif
#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
#include "southbridge/intel/i82801gx/nvs.h"
static void acpi_create_gnvs(global_nvs_t *gnvs)
{
memset((void *)gnvs, 0, sizeof(*gnvs));

2
src/mainboard/kontron/986lcd-m/mainboard_smi.c
View File

@ -21,7 +21,7 @@
#include <arch/romcc_io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
#include "southbridge/intel/i82801gx/nvs.h"
/* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler

4
src/mainboard/kontron/kt690/romstage.c
View File

@ -45,8 +45,8 @@
#include <cpu/amd/mtrr.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
#include "southbridge/amd/rs690/early_setup.c"
#include "southbridge/amd/sb600/early_setup.c"
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }

2
src/mainboard/lanner/em8510/romstage.c
View File

@ -33,7 +33,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "southbridge/intel/i82801dx/i82801dx.h"
#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
#include "southbridge/intel/i82801dx/early_smbus.c"
#include "northbridge/intel/i855/raminit.h"
#include "northbridge/intel/i855/debug.c"
#include "superio/winbond/w83627thg/w83627thg_early_serial.c"

4
src/mainboard/lippert/frontrunner/romstage.c
View File

@ -11,8 +11,8 @@
#include <cpu/amd/gx2def.h>
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5535/cs5535.h"
#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
#include "southbridge/amd/cs5535/cs5535_early_setup.c"
#include "southbridge/amd/cs5535/early_smbus.c"
#include "southbridge/amd/cs5535/early_setup.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

4
src/mainboard/lippert/hurricane-lx/romstage.c
View File

@ -34,8 +34,8 @@
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
/* Bit0 enables Spread Spectrum. */

4
src/mainboard/lippert/literunner-lx/romstage.c
View File

@ -34,8 +34,8 @@
#include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
/* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */

4
src/mainboard/lippert/roadrunner-lx/romstage.c
View File

@ -34,8 +34,8 @@
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
#define ManualConf 1 /* No automatic strapped PLL config */

4
src/mainboard/lippert/spacerunner-lx/romstage.c
View File

@ -34,8 +34,8 @@
#include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
/* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */

6
src/mainboard/msi/ms7135/romstage.c
View File

@ -36,7 +36,7 @@
#include <cpu/amd/model_fxx_rev.h>
#include <console/console.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
#include "southbridge/nvidia/ck804/early_smbus.h"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -60,8 +60,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
#include "southbridge/nvidia/ck804/early_setup_ss.h"
#include "southbridge/nvidia/ck804/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "northbridge/amd/amdk8/early_ht.c"

8
src/mainboard/msi/ms7260/romstage.c
View File

@ -36,7 +36,7 @@
#include <console/console.h>
#include <usbdebug.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
#include "southbridge/nvidia/mcp55/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -50,7 +50,7 @@
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
@ -78,8 +78,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
#include "southbridge/nvidia/mcp55/early_setup_ss.h"
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"

4
src/mainboard/msi/ms9185/romstage.c
View File

@ -34,7 +34,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
#include "southbridge/broadcom/bcm5785/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -46,7 +46,7 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
#include "southbridge/broadcom/bcm5785/early_setup.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)

8
src/mainboard/msi/ms9282/romstage.c
View File

@ -32,7 +32,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
#include "southbridge/nvidia/mcp55/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -45,7 +45,7 @@
#include <spd.h>
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <device/pci_ids.h>
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
@ -82,7 +82,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/early_setup_ss.h"
//set GPIO to input mode
#define MCP55_MB_SETUP \
@ -91,7 +91,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
// Disabled until it's actually used:

8
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@ -35,7 +35,7 @@
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
#include "southbridge/nvidia/mcp55/early_smbus.c"
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "cpu/amd/model_fxx/apic_timer.c"
@ -47,7 +47,7 @@
#include "northbridge/amd/amdfam10/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
@ -72,8 +72,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
#include "southbridge/nvidia/mcp55/early_setup_ss.h"
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"

4
src/mainboard/newisys/khepri/romstage.c
View File

@ -17,7 +17,7 @@
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "southbridge/amd/amd8111/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -28,7 +28,7 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

8
src/mainboard/nvidia/l1_2pvv/romstage.c
View File

@ -37,7 +37,7 @@
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
#include "southbridge/nvidia/mcp55/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -49,7 +49,7 @@
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
@ -77,8 +77,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
#include "southbridge/nvidia/mcp55/early_setup_ss.h"
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"

2
src/mainboard/pcengines/alix1c/romstage.c
View File

@ -38,7 +38,7 @@
/* The ALIX1.C has no SMBus; the setup is hard-wired. */
static void cs5536_enable_smbus(void) { }
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "southbridge/amd/cs5536/early_setup.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
/* The part is a Hynix hy5du121622ctp-d43.

2
src/mainboard/pcengines/alix2d/romstage.c
View File

@ -38,7 +38,7 @@
/* The ALIX.2D has no SMBus; the setup is hard-wired. */
static void cs5536_enable_smbus(void) { }
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "southbridge/amd/cs5536/early_setup.c"
/* The part is a Hynix hy5du121622ctp-d43.
*

6
src/mainboard/rca/rm4100/romstage.c
View File

@ -32,12 +32,12 @@
#include "northbridge/intel/i82830/raminit.h"
#include "northbridge/intel/i82830/memory_initialized.c"
#include "southbridge/intel/i82801dx/i82801dx.h"
#include "southbridge/intel/i82801dx/i82801dx_reset.c"
#include "southbridge/intel/i82801dx/reset.c"
#include "cpu/x86/bist.h"
#include "spd_table.h"
#include "gpio.c"
#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
#include "southbridge/intel/i82801dx/i82801dx_tco_timer.c"
#include "southbridge/intel/i82801dx/early_smbus.c"
#include "southbridge/intel/i82801dx/tco_timer.c"
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)

2
src/mainboard/roda/rk886ex/acpi_tables.c
View File

@ -91,7 +91,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
}
#endif
#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
#include "southbridge/intel/i82801gx/nvs.h"
static void acpi_create_gnvs(global_nvs_t *gnvs)
{
memset((void *)gnvs, 0, sizeof(*gnvs));

2
src/mainboard/roda/rk886ex/mainboard_smi.c
View File

@ -23,7 +23,7 @@
#include <arch/romcc_io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
#include "southbridge/intel/i82801gx/nvs.h"
/* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler

6
src/mainboard/sunw/ultra40/romstage.c
View File

@ -11,7 +11,7 @@
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
#include "southbridge/nvidia/ck804/early_smbus.h"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -54,7 +54,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
#include "southbridge/nvidia/ck804/early_setup_ss.h"
//set GPIO to input mode
#define CK804_MB_SETUP \
@ -65,7 +65,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
#include "southbridge/nvidia/ck804/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "northbridge/amd/amdk8/early_ht.c"

8
src/mainboard/supermicro/h8dme/romstage.c
View File

@ -33,7 +33,7 @@
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -45,7 +45,7 @@
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
@ -127,8 +127,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
#include "southbridge/nvidia/mcp55/early_setup_ss.h"
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"

8
src/mainboard/supermicro/h8dmr/romstage.c
View File

@ -36,7 +36,7 @@
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -48,7 +48,7 @@
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
@ -68,8 +68,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
#include "southbridge/nvidia/mcp55/early_setup_ss.h"
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"

8
src/mainboard/supermicro/h8dmr_fam10/romstage.c
View File

@ -34,7 +34,7 @@
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "cpu/amd/model_10xxx/apic_timer.c"
@ -47,7 +47,7 @@
#include "northbridge/amd/amdfam10/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
@ -64,8 +64,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
#include "southbridge/nvidia/mcp55/early_setup_ss.h"
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"

8
src/mainboard/supermicro/h8qme_fam10/romstage.c
View File

@ -34,7 +34,7 @@
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "cpu/amd/model_10xxx/apic_timer.c"
@ -47,7 +47,7 @@
#include "northbridge/amd/amdfam10/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
@ -70,8 +70,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
#include "southbridge/nvidia/mcp55/early_setup_ss.h"
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"

2
src/mainboard/supermicro/x6dai_g/romstage.c
View File

@ -8,7 +8,7 @@
#include <console/console.h>
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "southbridge/intel/esb6300/esb6300_early_smbus.c"
#include "southbridge/intel/esb6300/early_smbus.c"
#include "northbridge/intel/e7525/raminit.h"
#include "superio/winbond/w83627hf/w83627hf.h"
#include "cpu/x86/lapic/boot_cpu.c"

2
src/mainboard/supermicro/x6dhe_g/romstage.c
View File

@ -8,7 +8,7 @@
#include <console/console.h>
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "southbridge/intel/esb6300/esb6300_early_smbus.c"
#include "southbridge/intel/esb6300/early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
#include "superio/winbond/w83627hf/w83627hf.h"
#include "cpu/x86/lapic/boot_cpu.c"

2
src/mainboard/supermicro/x6dhe_g2/romstage.c
View File

@ -6,7 +6,7 @@
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include <console/console.h>
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "southbridge/intel/i82801ex/early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
#include "superio/nsc/pc87427/pc87427.h"
#include "cpu/x86/lapic/boot_cpu.c"

2
src/mainboard/supermicro/x6dhr_ig/romstage.c
View File

@ -6,7 +6,7 @@
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include <console/console.h>
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "southbridge/intel/i82801ex/early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
#include "superio/winbond/w83627hf/w83627hf.h"
#include "cpu/x86/lapic/boot_cpu.c"

2
src/mainboard/supermicro/x6dhr_ig2/romstage.c
View File

@ -6,7 +6,7 @@
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include <console/console.h>
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "southbridge/intel/i82801ex/early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
#include "superio/winbond/w83627hf/w83627hf.h"
#include "cpu/x86/lapic/boot_cpu.c"

4
src/mainboard/technexion/tim5690/romstage.c
View File

@ -44,8 +44,8 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
#include "southbridge/amd/rs690/early_setup.c"
#include "southbridge/amd/sb600/early_setup.c"
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }

4
src/mainboard/technexion/tim8690/romstage.c
View File

@ -44,8 +44,8 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
#include "southbridge/amd/rs690/early_setup.c"
#include "southbridge/amd/sb600/early_setup.c"
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }

2
src/mainboard/televideo/tc7020/romstage.c
View File

@ -28,7 +28,7 @@
#include "northbridge/amd/gx1/raminit.c"
#include "superio/nsc/pc97317/pc97317_early_serial.c"
#include "cpu/x86/bist.h"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#include "southbridge/amd/cs5530/enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)

6
src/mainboard/thomson/ip1000/romstage.c
View File

@ -33,12 +33,12 @@
#include "northbridge/intel/i82830/raminit.h"
#include "northbridge/intel/i82830/memory_initialized.c"
#include "southbridge/intel/i82801dx/i82801dx.h"
#include "southbridge/intel/i82801dx/i82801dx_reset.c"
#include "southbridge/intel/i82801dx/reset.c"
#include "cpu/x86/bist.h"
#include "spd_table.h"
#include "gpio.c"
#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
#include "southbridge/intel/i82801dx/i82801dx_tco_timer.c"
#include "southbridge/intel/i82801dx/early_smbus.c"
#include "southbridge/intel/i82801dx/tco_timer.c"
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)

4
src/mainboard/traverse/geos/romstage.c
View File

@ -32,8 +32,8 @@
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
static inline int spd_read_byte(unsigned int device, unsigned int address)
{

2
src/mainboard/tyan/s2735/romstage.c
View File

@ -9,7 +9,7 @@
#include <console/console.h>
#include <lib.h>
#include <spd.h>
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "southbridge/intel/i82801ex/early_smbus.c"
#include "northbridge/intel/e7501/raminit.h"
#include "northbridge/intel/e7501/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"

4
src/mainboard/tyan/s2850/romstage.c
View File

@ -12,7 +12,7 @@
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "southbridge/amd/amd8111/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -23,7 +23,7 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

4
src/mainboard/tyan/s2875/romstage.c
View File

@ -12,7 +12,7 @@
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "southbridge/amd/amd8111/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -23,7 +23,7 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

4
src/mainboard/tyan/s2880/romstage.c
View File

@ -12,7 +12,7 @@
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "southbridge/amd/amd8111/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@ -23,7 +23,7 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

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