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Following patch fills in the callbacks for PCIe x16 resets. This board uses GPM8,GPM9 as reset toggles. 

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Rudolf Marek 2011-02-26 19:46:08 +00:00
parent 656060d1d9
commit 837403dddf
1 changed files with 19 additions and 0 deletions
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19
src/mainboard/asrock/939a785gmh/mainboard.c
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@ -35,12 +35,31 @@ uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void); void set_pcie_dereset(void);
void set_pcie_reset(void); void set_pcie_reset(void);
u8 is_dev3_present(void); u8 is_dev3_present(void);
static void pcie_rst_toggle(u8 val) {
u8 byte;
byte = pm_ioread(0x8d);
byte &= ~(3 << 1);
pm_iowrite(0x8d, byte);
byte = pm_ioread(0x94);
/* Output enable */
byte &= ~(3 << 2);
/* Toggle GPM8, GPM9 */
byte &= ~(3 << 0);
byte |= val;
pm_iowrite(0x94, byte);
}
void set_pcie_dereset() void set_pcie_dereset()
{ {
pcie_rst_toggle(0x3);
} }
void set_pcie_reset() void set_pcie_reset()
{ {
pcie_rst_toggle(0x0);
} }
#if 0 /* not tested yet */ #if 0 /* not tested yet */