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soc/intel/alderlake: Add known CPU Port IDs for GPIO communities 

Change-Id: Id5fa5b10edeb3445a2d2453d9122376041577598
Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Deepti Deshatty 2021-05-12 16:09:07 +05:30 committed by Patrick Georgi
parent f35be77ee3
commit 8386e7cd5b
2 changed files with 11 additions and 0 deletions
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5
src/soc/intel/alderlake/gpio.c
View File

@ -69,6 +69,7 @@ static const struct pad_group adl_community5_groups[] = {
static const struct pad_community adl_communities[] = { static const struct pad_community adl_communities[] = {
[COMM_0] = { /* GPP B, T, A */ [COMM_0] = { /* GPP B, T, A */
.port = PID_GPIOCOM0, .port = PID_GPIOCOM0,
.cpu_port = PID_CPU_GPIOCOM0,
.first_pad = GPIO_COM0_START, .first_pad = GPIO_COM0_START,
.last_pad = GPIO_COM0_END, .last_pad = GPIO_COM0_END,
.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
@ -88,6 +89,7 @@ static const struct pad_community adl_communities[] = {
}, },
[COMM_1] = { /* GPP S, D, H */ [COMM_1] = { /* GPP S, D, H */
.port = PID_GPIOCOM1, .port = PID_GPIOCOM1,
.cpu_port = PID_CPU_GPIOCOM1,
.first_pad = GPIO_COM1_START, .first_pad = GPIO_COM1_START,
.last_pad = GPIO_COM1_END, .last_pad = GPIO_COM1_END,
.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
@ -126,6 +128,7 @@ static const struct pad_community adl_communities[] = {
}, },
[COMM_3] = { /* vGPIO */ [COMM_3] = { /* vGPIO */
.port = PID_GPIOCOM3, .port = PID_GPIOCOM3,
.cpu_port = PID_CPU_GPIOCOM3,
.first_pad = GPIO_COM3_START, .first_pad = GPIO_COM3_START,
.last_pad = GPIO_COM3_END, .last_pad = GPIO_COM3_END,
.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
@ -145,6 +148,7 @@ static const struct pad_community adl_communities[] = {
}, },
[COMM_4] = { /* GPP F, C, HVMOS, E */ [COMM_4] = { /* GPP F, C, HVMOS, E */
.port = PID_GPIOCOM4, .port = PID_GPIOCOM4,
.cpu_port = PID_CPU_GPIOCOM4,
.first_pad = GPIO_COM4_START, .first_pad = GPIO_COM4_START,
.last_pad = GPIO_COM4_END, .last_pad = GPIO_COM4_END,
.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
@ -164,6 +168,7 @@ static const struct pad_community adl_communities[] = {
}, },
[COMM_5] = { /* GPP R, SPI0 */ [COMM_5] = { /* GPP R, SPI0 */
.port = PID_GPIOCOM5, .port = PID_GPIOCOM5,
.cpu_port = PID_CPU_GPIOCOM5,
.first_pad = GPIO_COM5_START, .first_pad = GPIO_COM5_START,
.last_pad = GPIO_COM5_END, .last_pad = GPIO_COM5_END,
.num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,

6
src/soc/intel/alderlake/include/soc/pcr_ids.h
View File

@ -33,6 +33,12 @@
#define PID_ITSS 0xc4 #define PID_ITSS 0xc4
#define PID_SERIALIO 0xcb #define PID_SERIALIO 0xcb
/* CPU Port IDs */
#define PID_CPU_GPIOCOM0 0xb7
#define PID_CPU_GPIOCOM1 0xb8
#define PID_CPU_GPIOCOM3 0xbb
#define PID_CPU_GPIOCOM4 0xb9
#define PID_CPU_GPIOCOM5 0xba
/* /*
* SPI - DMI Destination ID * SPI - DMI Destination ID