AMD Bettong: refactor PCI interrupt table
1. Use write_pci_int_table to write registers 0xC00/0xC01. 2. Add GPIO, I2C and UART interrupt according "BKDG for AMD Family 15h Models 60h-6Fh Processors", 50742 Rev 3.01 - July 17, 2015 3. The interrupt valudes are moved from bettong/mptable.c. All devices work in Windows 10. Change-Id: Iad13bc02c84a5dfc7c24356436ac560f593304d7 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/11746 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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parent
1bb4083859
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src
mainboard/amd/bettong
southbridge/amd/pi/hudson
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@ -17,6 +17,65 @@
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#include <device/device.h>
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#include <arch/acpi.h>
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#include <agesawrapper.h>
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#include <southbridge/amd/common/amd_pci_util.h>
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/***********************************************************
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* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
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* This table is responsible for physically routing the PIC and
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* IOAPIC IRQs to the different PCI devices on the system. It
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* is read and written via registers 0xC00/0xC01 as an
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* Index/Data pair. These values are chipset and mainboard
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* dependent and should be updated accordingly.
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*
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* These values are used by the PCI configuration space,
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* MP Tables. TODO: Make ACPI use these values too.
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*/
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const u8 mainboard_picr_data[] = {
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[0x00] = 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,
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[0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
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[0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,
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[0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
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[0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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[0x30] = 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,
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[0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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[0x40] = 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,
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[0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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[0x50] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F,
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[0x58] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
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[0x60] = 0x1F,0x1F,0x07,0x1F,0x1F,0x1F,0x1F,0x1F,
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[0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
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[0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F,
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[0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
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};
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const u8 mainboard_intr_data[] = {
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[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
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[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
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[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10,
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[0x18] = 0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,
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[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
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[0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,
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[0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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[0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
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[0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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[0x50] = 0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,
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[0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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[0x60] = 0x1F,0x1F,0x07,0x00,0x00,0x00,0x00,0x00,
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[0x68] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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[0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F,
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[0x78] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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};
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/* PIRQ Setup */
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static void pirq_setup(void)
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{
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intr_data_ptr = mainboard_intr_data;
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picr_data_ptr = mainboard_picr_data;
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}
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/*************************************************
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* enable the dedicated function in bettong board.
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@ -27,6 +86,9 @@ static void bettong_enable(device_t dev)
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if (acpi_is_wakeup_s3())
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agesawrapper_fchs3earlyrestore();
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/* Initialize the PIRQ data structures for consumption */
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pirq_setup();
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}
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struct chip_operations mainboard_ops = {
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@ -24,23 +24,7 @@
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#include <arch/cpu.h>
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#include <cpu/x86/lapic.h>
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#include "southbridge/amd/pi/hudson/hudson.h" /* pm_ioread() */
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u8 picr_data[0x54] = {
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0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
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0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x03,0x04,0x05,0x07
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};
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u8 intr_data[0x54] = {
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0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
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0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x10,0x11,0x12,0x13
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};
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#include <southbridge/amd/common/amd_pci_util.h>
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static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
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{
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{
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struct mp_config_table *mc;
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int bus_isa;
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u8 byte;
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/*
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* By the time this function gets called, the IOAPIC registers
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@ -91,17 +74,6 @@ static void *smp_write_config_table(void *v)
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smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
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smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
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/* PIC IRQ routine */
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for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
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outb(byte, 0xC00);
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outb(picr_data[byte], 0xC01);
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}
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/* APIC IRQ routine */
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for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
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outb(byte | 0x80, 0xC00);
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outb(intr_data[byte], 0xC01);
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}
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/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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#define IO_LOCAL_INT(type, intr, apicid, pin) \
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
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/* Internal VGA */
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PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
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PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
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PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
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PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
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/* SMBUS */
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PCI_INT(0x0, 0x14, 0x0, 0x10);
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/* HD Audio */
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PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
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PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
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/* USB */
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PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
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PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
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PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
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PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
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PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
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PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
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PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
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PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
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PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
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PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
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PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
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PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
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PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
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PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
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/* sata */
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PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
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PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
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PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
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PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
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/* on board NIC & Slot PCIE. */
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@ -77,8 +77,14 @@
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#endif
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#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
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#define FCH_INT_TABLE_SIZE 0x75
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#define FCH_INT_TABLE_SIZE 0x76
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#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */
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#define PIRQ_I2C0 0x70
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#define PIRQ_I2C1 0x71
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#define PIRQ_I2C2 0x72
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#define PIRQ_I2C3 0x73
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#define PIRQ_UART0 0x74
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#define PIRQ_UART1 0x75
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#endif
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#endif /* AMD_PCI_INT_DEFS_H */
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#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
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[0x40] = "IDE\t", "SATA\t",
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[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t",
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[0x75] = NULL
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[0x62] = "GPIO\t",
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[0x70] = "I2C0\t", "I2C1\t", "I2C2\t","I2C3\t", "UART0\t", "UART1\t",
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#endif
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};
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