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drop __ROMCC__ define checks.. __PRE_RAM__ is what the code should be looking for. 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-03-28 15:11:56 +00:00 committed by Stefan Reinauer
parent f733d47544
commit 83a1dd850b
7 changed files with 7 additions and 10 deletions
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2
src/southbridge/amd/cs5530/cs5530.h
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@ -21,7 +21,7 @@
#ifndef SOUTHBRIDGE_AMD_CS5530_CS5530_H
#define SOUTHBRIDGE_AMD_CS5530_CS5530_H
#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
#if !defined(__PRE_RAM__)
#include "chip.h"
void cs5530_enable(device_t dev);
#endif

2
src/southbridge/intel/i82371eb/i82371eb.h
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@ -21,7 +21,7 @@
#ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
#define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
#if !defined(__PRE_RAM__)
#include "chip.h"
void i82371eb_enable(device_t dev);
void i82371eb_hard_reset(void);

2
src/southbridge/intel/i82801ax/i82801ax.h
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@ -21,7 +21,7 @@
#ifndef SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H
#define SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H
#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
#if !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801ax_enable(device_t dev);
#endif

2
src/southbridge/intel/i82801bx/i82801bx.h
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@ -21,7 +21,7 @@
#ifndef SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H
#define SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H
#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
#if !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801bx_enable(device_t dev);
#endif

2
src/southbridge/intel/i82801cx/i82801cx.h
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@ -1,7 +1,7 @@
#ifndef I82801CX_H
#define I82801CX_H
#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
#if !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801cx_enable(device_t dev);
#endif

2
src/southbridge/intel/i82801dx/i82801dx.h
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@ -31,7 +31,7 @@
#ifndef I82801DX_H
#define I82801DX_H
#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
#if !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801dx_enable(device_t dev);
#endif

5
src/southbridge/intel/i82801gx/i82801gx.h
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@ -39,10 +39,7 @@
#ifndef __ACPI__
#define DEBUG_PERIODIC_SMIS 0
/* __ROMCC__ is set by romstage.c to make sure
* none of the stage2 data structures are included.
*/
#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
#if !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801gx_enable(device_t dev);
#endif