From 83a55930ddedb38c603383a799ea3f40034b6df1 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 25 Mar 2021 15:59:49 +0100 Subject: [PATCH] soc/intel/xeon_sp: Prepare for CBnT BPM generation To generate a working BPM, boot policy manifest for Intel CBnT the tool that generates it, requires ACPI base and PCH PWRM base as input. Therefore make it a Kconfig symbol, that can be used in Makefile.inc. Change-Id: I6f1f9b53e34114682bd3258753f2d5aada9a530d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/51805 Reviewed-by: Angel Pons Reviewed-by: Christian Walter Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/Kconfig | 12 ++++++++++++ src/soc/intel/xeon_sp/include/soc/iomap.h | 4 ++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 44028bead5..61ab75090b 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -82,6 +82,18 @@ config MAX_CPUS int default 80 +config INTEL_ACPI_BASE_ADDRESS + hex + default 0x500 + help + IO Address of ACPI. + +config INTEL_PCH_PWRM_BASE_ADDRESS + hex + default 0xfe000000 + help + PCH PWRM Base address. + config PCR_BASE_ADDRESS hex default 0xfd000000 diff --git a/src/soc/intel/xeon_sp/include/soc/iomap.h b/src/soc/intel/xeon_sp/include/soc/iomap.h index 2df5f8bfe1..ceaf271eb2 100644 --- a/src/soc/intel/xeon_sp/include/soc/iomap.h +++ b/src/soc/intel/xeon_sp/include/soc/iomap.h @@ -19,7 +19,7 @@ #define SPI_BASE_SIZE 0x1000 #define TCO_BASE_ADDRESS 0x400 -#define ACPI_BASE_ADDRESS 0x500 +#define ACPI_BASE_ADDRESS CONFIG_INTEL_ACPI_BASE_ADDRESS #define ACPI_BASE_SIZE 0x100 /* Video RAM */ @@ -31,7 +31,7 @@ #define HECI1_BASE_ADDRESS 0xfed1a000 -#define PCH_PWRM_BASE_ADDRESS 0xfe000000 +#define PCH_PWRM_BASE_ADDRESS CONFIG_INTEL_PCH_PWRM_BASE_ADDRESS #define PCH_PWRM_BASE_SIZE 0x10000 #define P2SB_BAR CONFIG_PCR_BASE_ADDRESS