From 83abfdfb212e66e96bc400f7d45f25037b34e42e Mon Sep 17 00:00:00 2001 From: Vaibhav Shankar Date: Wed, 21 Mar 2018 17:06:18 -0700 Subject: [PATCH] mainboard/google/meowth: Disable debug consent and enable S0ix This patch disables debug consent in the devicetree. When debug consent is set to DBC by default, it prevents some clocks from turning off during S0ix. This blocks S0ix entry. This patch also enables S0ix from the devicetree. BUG=b:76163091 TEST=enter S0ix and check if slp_s0 is asserted Change-Id: I05001a41b13e7784c34fa8f1f773fb94bbdcd01f Signed-off-by: Vaibhav Shankar Reviewed-on: https://review.coreboot.org/25312 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../google/zoombini/variants/meowth/devicetree.cb | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index 062c6ecb78..4076ea6035 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -6,8 +6,8 @@ chip soc/intel/cannonlake register "deep_s5_enable_ac" = "1" register "deep_s5_enable_dc" = "1" - # Debug Option, set to DBC over USB 3.0 port only - register "DebugConsent" = "DebugConsent_USB3_DBC" + # Debug Option + register "DebugConsent" = "DebugConsent_Disabled" # GPE configuration # Note that GPE events called out in ASL code rely on this @@ -75,6 +75,9 @@ chip soc/intel/cannonlake register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" + # Enable S0ix + register "s0ix_enable" = "1" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device