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mainboard/google/meowth: Disable debug consent and enable S0ix 

This patch disables debug consent in the devicetree. When debug
consent is set to DBC by default, it prevents some clocks from turning
off during S0ix. This blocks S0ix entry.

This patch also enables S0ix from the devicetree.

BUG=b:76163091
TEST=enter S0ix and check if slp_s0 is asserted

Change-Id: I05001a41b13e7784c34fa8f1f773fb94bbdcd01f
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/25312
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Vaibhav Shankar 2018-03-21 17:06:18 -07:00 committed by Patrick Georgi
parent f47c2c5ce6
commit 83abfdfb21
1 changed files with 5 additions and 2 deletions
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7
src/mainboard/google/zoombini/variants/meowth/devicetree.cb
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@ -6,8 +6,8 @@ chip soc/intel/cannonlake
register "deep_s5_enable_ac" = "1" register "deep_s5_enable_ac" = "1"
register "deep_s5_enable_dc" = "1" register "deep_s5_enable_dc" = "1"
# Debug Option, set to DBC over USB 3.0 port only # Debug Option
register "DebugConsent" = "DebugConsent_USB3_DBC" register "DebugConsent" = "DebugConsent_Disabled"
# GPE configuration # GPE configuration
# Note that GPE events called out in ASL code rely on this # Note that GPE events called out in ASL code rely on this
@ -75,6 +75,9 @@ chip soc/intel/cannonlake
register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcUsage[3]" = "8"
register "PcieClkSrcClkReq[3]" = "3" register "PcieClkSrcClkReq[3]" = "3"
# Enable S0ix
register "s0ix_enable" = "1"
device domain 0 on device domain 0 on
device pci 00.0 on end # Host Bridge device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device device pci 02.0 on end # Integrated Graphics Device