acpi: Upgrade acpi generate header
Sync acpigen.h content to match with laetst acpica, the link is https://github.com/acpica/acpica/blob/master/source/include/amlcode.h, and revision is 20190405. The purspose of the change is just make spec up to date. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: If5f5da70eb66472ddf5df0d72ca85de41faac128 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -42,29 +42,57 @@
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/* ACPI Op/Prefix Codes */
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enum {
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ZERO_OP = 0x00,
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ZERO_OP = 0x00,
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ONE_OP = 0x01,
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NAME_OP = 0x08,
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SCOPE_OP = 0x10,
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BUFFER_OP = 0x11,
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ALIAS_OP = 0x06,
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NAME_OP = 0x08,
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BYTE_PREFIX = 0x0A,
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WORD_PREFIX = 0x0B,
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DWORD_PREFIX = 0x0C,
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STRING_PREFIX = 0x0D,
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QWORD_PREFIX = 0x0E,
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SCOPE_OP = 0x10,
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BUFFER_OP = 0x11,
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PACKAGE_OP = 0x12,
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VARIABLE_PACKAGE_OP = 0x13,
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METHOD_OP = 0x14,
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EXTERNAL_OP = 0x15,
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DUAL_NAME_PREFIX = 0x2E,
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MULTI_NAME_PREFIX = 0x2F,
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EXT_OP_PREFIX = 0x5B,
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MUTEX_OP = 0x01,
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EVENT_OP = 0x01,
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SF_RIGHT_OP = 0x10,
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SF_LEFT_OP = 0x11,
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COND_REFOF_OP = 0x12,
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CREATEFIELD_OP = 0x13,
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LOAD_TABLE_OP = 0x1f,
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LOAD_OP = 0x20,
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STALL_OP = 0x21,
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SLEEP_OP = 0x22,
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ACQUIRE_OP = 0x23,
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SIGNAL_OP = 0x24,
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WAIT_OP = 0x25,
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RST_OP = 0x26,
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RELEASE_OP = 0x27,
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FROM_BCD_OP = 0x28,
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TO_BCD_OP = 0x29,
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UNLOAD_OP = 0x2A,
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REVISON_OP = 0x30,
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DEBUG_OP = 0x31,
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FATAL_OP = 0x32,
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TIMER_OP = 0x33,
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OPREGION_OP = 0x80,
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FIELD_OP = 0x81,
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DEVICE_OP = 0x82,
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PROCESSOR_OP = 0x83,
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POWER_RES_OP = 0x84,
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THERMAL_ZONE_OP = 0x85,
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INDEX_FIELD_OP = 0x86,
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BANK_FIELD_OP = 0x87,
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DATA_REGION_OP = 0x88,
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ROOT_PREFIX = 0x5C,
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PARENT_PREFIX = 0x5D,
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LOCAL0_OP = 0x60,
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LOCAL1_OP = 0x61,
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LOCAL2_OP = 0x62,
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@ -73,29 +101,68 @@ enum {
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LOCAL5_OP = 0x65,
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LOCAL6_OP = 0x66,
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LOCAL7_OP = 0x67,
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ARG0_OP = 0x68,
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ARG1_OP = 0x69,
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ARG2_OP = 0x6A,
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ARG3_OP = 0x6B,
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ARG4_OP = 0x6C,
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ARG5_OP = 0x6D,
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ARG6_OP = 0x6E,
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ARG0_OP = 0x68,
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ARG1_OP = 0x69,
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ARG2_OP = 0x6A,
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ARG3_OP = 0x6B,
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ARG4_OP = 0x6C,
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ARG5_OP = 0x6D,
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ARG6_OP = 0x6E,
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STORE_OP = 0x70,
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REF_OF_OP = 0x71,
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ADD_OP = 0x72,
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CONCATENATE_OP = 0x73,
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SUBTRACT_OP = 0x74,
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INCREMENT_OP = 0x75,
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DECREMENT_OP = 0x76,
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MULTIPLY_OP = 0x77,
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DIVIDE_OP = 0x78,
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SHIFT_LEFT_OP = 0x79,
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SHIFT_RIGHT_OP = 0x7A,
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AND_OP = 0x7B,
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NAND_OP = 0x7C,
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OR_OP = 0x7D,
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NOR_OP = 0x7E,
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XOR_OP = 0x7F,
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NOT_OP = 0x80,
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FD_SHIFT_LEFT_BIT_OR = 0x81,
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FD_SHIFT_RIGHT_BIT_OR = 0x82,
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DEREF_OP = 0x83,
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CONCATENATE_TEMP_OP = 0x84,
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MOD_OP = 0x85,
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NOTIFY_OP = 0x86,
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SIZEOF_OP = 0x87,
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INDEX_OP = 0x88,
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MATCH_OP = 0x89,
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CREATE_DWORD_OP = 0x8A,
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CREATE_WORD_OP = 0x8B,
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CREATE_BYTE_OP = 0x8C,
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CREATE_BIT_OP = 0x8D,
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OBJ_TYPE_OP = 0x8E,
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CREATE_QWORD_OP = 0x8F,
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LAND_OP = 0x90,
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LOR_OP = 0x91,
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LNOT_OP = 0x92,
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LEQUAL_OP = 0x93,
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LGREATER_OP = 0x94,
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LLESS_OP = 0x95,
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TO_BUFFER_OP = 0x96,
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TO_DEC_STRING_OP = 0x97,
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TO_HEX_STRING_OP = 0x98,
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TO_INTEGER_OP = 0x99,
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TO_STRING_OP = 0x9C,
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CP_OBJ_OP = 0x9D,
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MID_OP = 0x9E,
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CONTINUE_OP = 0x9F,
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IF_OP = 0xA0,
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ELSE_OP = 0xA1,
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ELSE_OP = 0xA1,
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WHILE_OP = 0xA2,
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NOOP_OP = 0xA3,
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RETURN_OP = 0xA4,
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ONES_OP = 0xFF,
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BREAK_OP = 0xA5,
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COMMENT_OP = 0xA9,
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BREAKPIONT_OP = 0xCC,
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ONES_OP = 0xFF,
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};
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#define FIELDLIST_OFFSET(X) { .type = OFFSET, \
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@ -146,6 +213,10 @@ enum region_space {
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CMOS,
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PCIBARTARGET,
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IPMI,
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GPIO_REGION,
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GPSERIALBUS,
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PCC,
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FIXED_HARDWARE = 0x7F,
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REGION_SPACE_MAX,
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};
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