google/butterfly: Drop MRC.bin in favor of native raminit
I thought this wasn't going to work, and observing the timC detection failure of early tests, I was getting somewhat discouraged; however, this works. I've tried it with all possible permutations of the following memory modules: * 2 GiB single-rank DDR3-1600 * 4 GiB single-rank DDR3-1600 * 4 GiB dual-rank DDR3-1600 I did notice a limited number of memtest errors during one of the runs, but they were in an address range that is otherwise marked as reserved. I wrote that off as "maybe something was doing MMIO there just when memtest was poking the address range". I was not able to reproduce that error. Change-Id: Ibd52e1d52fc8d900591d6a488f9a5b4d1e5e4fd3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8477 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
This commit is contained in:
Alexandru Gagniuc
parent
21d898bad0
commit
83b05eb0a8
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@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select SYSTEM_TYPE_LAPTOP
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_IVYBRIDGE
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select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
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select SOUTHBRIDGE_INTEL_C216
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select EC_QUANTA_ENE_KB3940Q
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select BOARD_ROMSIZE_KB_8192
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@ -21,5 +21,6 @@ ramstage-y += ec.c
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romstage-y += chromeos.c
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ramstage-y += chromeos.c
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romstage-y += gpio.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
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@ -12,6 +12,8 @@ chip northbridge/intel/sandybridge
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register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms
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register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
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register "max_mem_clock_mhz" = "666" # DDR3-1333
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0 on end
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@ -17,9 +17,6 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef BUTTERFLY_GPIO_H
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#define BUTTERFLY_GPIO_H
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#include "southbridge/intel/bd82x6x/gpio.h"
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const struct pch_gpio_set1 pch_gpio_set1_mode = {
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@ -282,7 +279,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = {
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.gpio75 = GPIO_LEVEL_LOW, /* Input */
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};
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const struct pch_gpio_map butterfly_gpio_map = {
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const struct pch_gpio_map mainboard_gpio_map = {
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.set1 = {
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.mode = &pch_gpio_set1_mode,
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.direction = &pch_gpio_set1_direction,
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@ -301,4 +298,3 @@ const struct pch_gpio_map butterfly_gpio_map = {
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.level = &pch_gpio_set3_level,
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},
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};
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#endif
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@ -32,20 +32,18 @@
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#include <cbmem.h>
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#include <console/console.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/gpio.h>
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#include <arch/cpu.h>
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#include <cpu/x86/bist.h>
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#include <cpu/x86/msr.h>
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#include <halt.h>
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#include "gpio.h"
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#if CONFIG_CHROMEOS
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#include <vendorcode/google/chromeos/chromeos.h>
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#endif
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#include <cbfs.h>
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static void pch_enable_lpc(void)
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void pch_enable_lpc(void)
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{
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/* EC Decode Range Port60/64 and Port62/66 */
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/* Enable EC and PS/2 Keyboard/Mouse*/
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@ -59,7 +57,7 @@ static void pch_enable_lpc(void)
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}
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static void rcba_config(void)
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void rcba_config(void)
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{
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u32 reg32;
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@ -73,134 +71,25 @@ static void rcba_config(void)
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RCBA32(FD) = reg32;
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}
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#include <cpu/intel/romstage.h>
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void main(unsigned long bist)
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{
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int boot_mode = 0;
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int cbmem_was_initted;
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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/* enabled usb oc pin length */
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{ 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */
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{ 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */
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{ 1, 0, 0x0040 }, /* P2: Camera (no OC) */
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{ 0, 0, 0x0000 }, /* P3: Empty */
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{ 0, 0, 0x0000 }, /* P4: Empty */
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{ 0, 0, 0x0000 }, /* P5: Empty */
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{ 0, 0, 0x0000 }, /* P6: Empty */
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{ 0, 0, 0x0000 }, /* P7: Empty */
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{ 0, 4, 0x0000 }, /* P8: Empty */
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{ 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */
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{ 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */
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{ 0, 4, 0x0000 }, /* P11: Empty */
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{ 0, 4, 0x0000 }, /* P12: Empty */
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{ 0, 4, 0x0000 }, /* P13: Empty */
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};
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struct pei_data pei_data = {
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.pei_version = PEI_VERSION,
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.mchbar = (uintptr_t)DEFAULT_MCHBAR,
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.dmibar = (uintptr_t)DEFAULT_DMIBAR,
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.epbar = DEFAULT_EPBAR,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.smbusbar = SMBUS_IO_BASE,
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.wdbbar = 0x4000000,
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.wdbsize = 0x1000,
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.hpet_address = CONFIG_HPET_ADDRESS,
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.rcba = (uintptr_t)DEFAULT_RCBABASE,
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.pmbase = DEFAULT_PMBASE,
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.gpiobase = DEFAULT_GPIOBASE,
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.thermalbase = 0xfed08000,
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.system_type = 0, // 0 Mobile, 1 Desktop/Server
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.tseg_size = CONFIG_SMM_TSEG_SIZE,
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.spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
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.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
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.ec_present = 1,
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.ddr3lv_support = 0,
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// 0 = leave channel enabled
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// 1 = disable dimm 0 on channel
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// 2 = disable dimm 1 on channel
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// 3 = disable dimm 0+1 on channel
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.dimm_channel0_disabled = 2,
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.dimm_channel1_disabled = 2,
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.max_ddr3_freq = 1600,
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.usb_port_config = {
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/* enabled usb oc pin length */
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{ 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */
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{ 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */
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{ 1, 0, 0x0040 }, /* P2: Camera (no OC) */
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{ 0, 0, 0x0000 }, /* P3: Empty */
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{ 0, 0, 0x0000 }, /* P4: Empty */
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{ 0, 0, 0x0000 }, /* P5: Empty */
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{ 0, 0, 0x0000 }, /* P6: Empty */
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{ 0, 0, 0x0000 }, /* P7: Empty */
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{ 0, 4, 0x0000 }, /* P8: Empty */
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{ 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */
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{ 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */
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{ 0, 4, 0x0000 }, /* P11: Empty */
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{ 0, 4, 0x0000 }, /* P12: Empty */
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{ 0, 4, 0x0000 }, /* P13: Empty */
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},
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.ddr_refresh_rate_config = 2, /* Force double refresh rate */
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};
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timestamp_init(get_initial_timestamp());
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timestamp_add_now(TS_START_ROMSTAGE);
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if (bist == 0)
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enable_lapic();
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pch_enable_lpc();
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/* Enable GPIOs */
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pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
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pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
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setup_pch_gpios(&butterfly_gpio_map);
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/* Initialize console device(s) */
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console_init();
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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if (MCHBAR16(SSKPD) == 0xCAFE) {
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printk(BIOS_DEBUG, "soft reset detected\n");
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boot_mode = 1;
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/* System is not happy after keyboard reset... */
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printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
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outb(0x6, 0xcf9);
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halt();
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}
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/* Perform some early chipset initialization required
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* before RAM initialization can work
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*/
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sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
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printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
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boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
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post_code(0x38);
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/* Enable SPD ROMs and DDR-III DRAM */
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enable_smbus();
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/* Prepare USB controller early in S3 resume */
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if (boot_mode == 2)
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enable_usb_bar();
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post_code(0x39);
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post_code(0x3a);
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pei_data.boot_mode = boot_mode;
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timestamp_add_now(TS_BEFORE_INITRAM);
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sdram_initialize(&pei_data);
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timestamp_add_now(TS_AFTER_INITRAM);
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post_code(0x3c);
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rcba_config();
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post_code(0x3d);
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quick_ram_check();
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post_code(0x3e);
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cbmem_was_initted = !cbmem_recovery(boot_mode==2);
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if (boot_mode!=2)
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save_mrc_data(&pei_data);
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if (boot_mode==2 && !cbmem_was_initted) {
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/* Failed S3 resume, reset to come up cleanly */
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outb(0x6, 0xcf9);
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halt();
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}
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northbridge_romstage_finalize(boot_mode==2);
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post_code(0x3f);
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#if CONFIG_CHROMEOS
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init_chromeos(boot_mode);
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#endif
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timestamp_add_now(TS_END_ROMSTAGE);
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void mainboard_get_spd(spd_raw_data *spd) {
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read_spd(&spd[0], 0x50);
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read_spd(&spd[2], 0x52);
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}
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