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google/butterfly: Drop MRC.bin in favor of native raminit 

I thought this wasn't going to work, and observing the timC detection
failure of early tests, I was getting somewhat discouraged; however,
this works. I've tried it with all possible permutations of the
following memory modules:
* 2 GiB single-rank DDR3-1600
* 4 GiB single-rank DDR3-1600
* 4 GiB dual-rank DDR3-1600

I did notice a limited number of memtest errors during one of the
runs, but they were in an address range that is otherwise marked as
reserved. I wrote that off as "maybe something was doing MMIO there
just when memtest was poking the address range". I was not able to
reproduce that error.

Change-Id: Ibd52e1d52fc8d900591d6a488f9a5b4d1e5e4fd3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8477
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
This commit is contained in:
Alexandru Gagniuc 2015-02-15 14:09:21 -06:00
parent 21d898bad0
commit 83b05eb0a8
5 changed files with 28 additions and 140 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/butterfly/Kconfig
View File

@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y def_bool y
select SYSTEM_TYPE_LAPTOP select SYSTEM_TYPE_LAPTOP
select CPU_INTEL_SOCKET_RPGA989 select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_IVYBRIDGE select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
select SOUTHBRIDGE_INTEL_C216 select SOUTHBRIDGE_INTEL_C216
select EC_QUANTA_ENE_KB3940Q select EC_QUANTA_ENE_KB3940Q
select BOARD_ROMSIZE_KB_8192 select BOARD_ROMSIZE_KB_8192

1
src/mainboard/google/butterfly/Makefile.inc
View File

@ -21,5 +21,6 @@ ramstage-y += ec.c
romstage-y += chromeos.c romstage-y += chromeos.c
ramstage-y += chromeos.c ramstage-y += chromeos.c
romstage-y += gpio.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c

2
src/mainboard/google/butterfly/devicetree.cb
View File

@ -12,6 +12,8 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms
register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
register "max_mem_clock_mhz" = "666" # DDR3-1333
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989 chip cpu/intel/socket_rPGA989
device lapic 0 on end device lapic 0 on end

6
src/mainboard/google/butterfly/gpio.h → src/mainboard/google/butterfly/gpio.c
View File

@ -17,9 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#ifndef BUTTERFLY_GPIO_H
#define BUTTERFLY_GPIO_H
#include "southbridge/intel/bd82x6x/gpio.h" #include "southbridge/intel/bd82x6x/gpio.h"
const struct pch_gpio_set1 pch_gpio_set1_mode = { const struct pch_gpio_set1 pch_gpio_set1_mode = {
@ -282,7 +279,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = {
.gpio75 = GPIO_LEVEL_LOW, /* Input */ .gpio75 = GPIO_LEVEL_LOW, /* Input */
}; };
const struct pch_gpio_map butterfly_gpio_map = { const struct pch_gpio_map mainboard_gpio_map = {
.set1 = { .set1 = {
.mode = &pch_gpio_set1_mode, .mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction, .direction = &pch_gpio_set1_direction,
@ -301,4 +298,3 @@ const struct pch_gpio_map butterfly_gpio_map = {
.level = &pch_gpio_set3_level, .level = &pch_gpio_set3_level,
}, },
}; };
#endif

127
src/mainboard/google/butterfly/romstage.c
View File

@ -32,20 +32,18 @@
#include <cbmem.h> #include <cbmem.h>
#include <console/console.h> #include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/bd82x6x/gpio.h> #include <southbridge/intel/bd82x6x/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <halt.h> #include <halt.h>
#include "gpio.h"
#if CONFIG_CHROMEOS #if CONFIG_CHROMEOS
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
#endif #endif
#include <cbfs.h> #include <cbfs.h>
static void pch_enable_lpc(void) void pch_enable_lpc(void)
{ {
/* EC Decode Range Port60/64 and Port62/66 */ /* EC Decode Range Port60/64 and Port62/66 */
/* Enable EC and PS/2 Keyboard/Mouse*/ /* Enable EC and PS/2 Keyboard/Mouse*/
@ -59,7 +57,7 @@ static void pch_enable_lpc(void)
} }
static void rcba_config(void) void rcba_config(void)
{ {
u32 reg32; u32 reg32;
@ -73,40 +71,7 @@ static void rcba_config(void)
RCBA32(FD) = reg32; RCBA32(FD) = reg32;
} }
#include <cpu/intel/romstage.h> const struct southbridge_usb_port mainboard_usb_ports[] = {
void main(unsigned long bist)
{
int boot_mode = 0;
int cbmem_was_initted;
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,
.system_type = 0, // 0 Mobile, 1 Desktop/Server
.tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
.ddr3lv_support = 0,
// 0 = leave channel enabled
// 1 = disable dimm 0 on channel
// 2 = disable dimm 1 on channel
// 3 = disable dimm 0+1 on channel
.dimm_channel0_disabled = 2,
.dimm_channel1_disabled = 2,
.max_ddr3_freq = 1600,
.usb_port_config = {
/* enabled usb oc pin length */ /* enabled usb oc pin length */
{ 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */
{ 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */
@ -122,85 +87,9 @@ void main(unsigned long bist)
{ 0, 4, 0x0000 }, /* P11: Empty */ { 0, 4, 0x0000 }, /* P11: Empty */
{ 0, 4, 0x0000 }, /* P12: Empty */ { 0, 4, 0x0000 }, /* P12: Empty */
{ 0, 4, 0x0000 }, /* P13: Empty */ { 0, 4, 0x0000 }, /* P13: Empty */
}, };
.ddr_refresh_rate_config = 2, /* Force double refresh rate */
};
timestamp_init(get_initial_timestamp()); void mainboard_get_spd(spd_raw_data *spd) {
timestamp_add_now(TS_START_ROMSTAGE); read_spd(&spd[0], 0x50);
read_spd(&spd[2], 0x52);
if (bist == 0)
enable_lapic();
pch_enable_lpc();
/* Enable GPIOs */
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&butterfly_gpio_map);
/* Initialize console device(s) */
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected\n");
boot_mode = 1;
/* System is not happy after keyboard reset... */
printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
outb(0x6, 0xcf9);
halt();
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
post_code(0x38);
/* Enable SPD ROMs and DDR-III DRAM */
enable_smbus();
/* Prepare USB controller early in S3 resume */
if (boot_mode == 2)
enable_usb_bar();
post_code(0x39);
post_code(0x3a);
pei_data.boot_mode = boot_mode;
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(&pei_data);
timestamp_add_now(TS_AFTER_INITRAM);
post_code(0x3c);
rcba_config();
post_code(0x3d);
quick_ram_check();
post_code(0x3e);
cbmem_was_initted = !cbmem_recovery(boot_mode==2);
if (boot_mode!=2)
save_mrc_data(&pei_data);
if (boot_mode==2 && !cbmem_was_initted) {
/* Failed S3 resume, reset to come up cleanly */
outb(0x6, 0xcf9);
halt();
}
northbridge_romstage_finalize(boot_mode==2);
post_code(0x3f);
#if CONFIG_CHROMEOS
init_chromeos(boot_mode);
#endif
timestamp_add_now(TS_END_ROMSTAGE);
} }