GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/tigerlake: Add PCIe root ports for PCH-H 

Change-Id: I89e300adce2edeb9d9c2bba1782c212ee656a532
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Jeremy Soller 2021-08-12 10:49:58 -06:00 committed by Felix Held
parent 21d7c477a4
commit 83d795c45b
3 changed files with 207 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

162
src/soc/intel/tigerlake/acpi/pcie.asl
View File

@ -54,7 +54,11 @@ Method (IRQM, 1, Serialized) {
Switch (ToInteger (Arg0)) Switch (ToInteger (Arg0))
{ {
Case (Package () { 1, 5, 9, 13 }) { Case (Package () { 1, 5, 9, 13
#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
, 17, 21
#endif
}) {
If (PICM) { If (PICM) {
Return (IQAA) Return (IQAA)
} Else { } Else {
@ -62,7 +66,11 @@ Method (IRQM, 1, Serialized) {
} }
} }
Case (Package () { 2, 6, 10, 14 }) { Case (Package () { 2, 6, 10, 14
#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
, 18, 22
#endif
}) {
If (PICM) { If (PICM) {
Return (IQBA) Return (IQBA)
} Else { } Else {
@ -70,7 +78,11 @@ Method (IRQM, 1, Serialized) {
} }
} }
Case (Package () { 3, 7, 11, 15 }) { Case (Package () { 3, 7, 11, 15
#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
, 19, 23
#endif
}) {
If (PICM) { If (PICM) {
Return (IQCA) Return (IQCA)
} Else { } Else {
@ -78,7 +90,11 @@ Method (IRQM, 1, Serialized) {
} }
} }
Case (Package () { 4, 8, 12, 16 }) { Case (Package () { 4, 8, 12, 16
#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
, 20, 24
#endif
}) {
If (PICM) { If (PICM) {
Return (IQDA) Return (IQDA)
} Else { } Else {
@ -299,3 +315,141 @@ Device (RP12)
Return (IRQM (RPPN)) Return (IRQM (RPPN))
} }
} }
#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
Device (RP17)
{
Name (_ADR, 0x001B0000)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP18)
{
Name (_ADR, 0x001B0001)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP19)
{
Name (_ADR, 0x001B0002)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP20)
{
Name (_ADR, 0x001B0003)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP21)
{
Name (_ADR, 0x001B0004)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP22)
{
Name (_ADR, 0x001B0005)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP23)
{
Name (_ADR, 0x001B0006)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP24)
{
Name (_ADR, 0x001B0007)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
#endif /* CONFIG(SOC_INTEL_TIGERLAKE_PCH_H) */

24
src/soc/intel/tigerlake/chip.c
View File

@ -23,6 +23,13 @@ static const struct pcie_rp_group pch_lp_rp_groups[] = {
{ 0 } { 0 }
}; };
static const struct pcie_rp_group pch_h_rp_groups[] = {
{ .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
{ .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 },
{ .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 },
{ 0 }
};
#if CONFIG(HAVE_ACPI_TABLES) #if CONFIG(HAVE_ACPI_TABLES)
const char *soc_acpi_name(const struct device *dev) const char *soc_acpi_name(const struct device *dev)
{ {
@ -93,6 +100,18 @@ const char *soc_acpi_name(const struct device *dev)
case PCH_DEVFN_PCIE10: return "RP10"; case PCH_DEVFN_PCIE10: return "RP10";
case PCH_DEVFN_PCIE11: return "RP11"; case PCH_DEVFN_PCIE11: return "RP11";
case PCH_DEVFN_PCIE12: return "RP12"; case PCH_DEVFN_PCIE12: return "RP12";
case PCH_DEVFN_PCIE13: return "RP13";
case PCH_DEVFN_PCIE14: return "RP14";
case PCH_DEVFN_PCIE15: return "RP15";
case PCH_DEVFN_PCIE16: return "RP16";
case PCH_DEVFN_PCIE17: return "RP17";
case PCH_DEVFN_PCIE18: return "RP18";
case PCH_DEVFN_PCIE19: return "RP19";
case PCH_DEVFN_PCIE20: return "RP20";
case PCH_DEVFN_PCIE21: return "RP21";
case PCH_DEVFN_PCIE22: return "RP22";
case PCH_DEVFN_PCIE23: return "RP23";
case PCH_DEVFN_PCIE24: return "RP24";
case PCH_DEVFN_PMC: return "PMC"; case PCH_DEVFN_PMC: return "PMC";
case PCH_DEVFN_UART0: return "UAR0"; case PCH_DEVFN_UART0: return "UAR0";
case PCH_DEVFN_UART1: return "UAR1"; case PCH_DEVFN_UART1: return "UAR1";
@ -135,7 +154,10 @@ void soc_init_pre_device(void *chip_info)
soc_fill_gpio_pm_configuration(); soc_fill_gpio_pm_configuration();
/* Swap enabled PCI ports in device tree if needed. */ /* Swap enabled PCI ports in device tree if needed. */
pcie_rp_update_devicetree(pch_lp_rp_groups); if (CONFIG(SOC_INTEL_TIGERLAKE_PCH_H))
pcie_rp_update_devicetree(pch_h_rp_groups);
else
pcie_rp_update_devicetree(pch_lp_rp_groups);
} }
static void cpu_fill_ssdt(const struct device *dev) static void cpu_fill_ssdt(const struct device *dev)

26
src/soc/intel/tigerlake/include/soc/pci_devs.h
View File

@ -163,10 +163,36 @@
#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) #define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1)
#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) #define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2)
#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) #define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3)
#define PCH_DEVFN_PCIE13 _PCH_DEVFN(PCIE_1, 4)
#define PCH_DEVFN_PCIE14 _PCH_DEVFN(PCIE_1, 5)
#define PCH_DEVFN_PCIE15 _PCH_DEVFN(PCIE_1, 6)
#define PCH_DEVFN_PCIE16 _PCH_DEVFN(PCIE_1, 7)
#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0) #define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0)
#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1) #define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1)
#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2) #define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2)
#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3) #define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3)
#define PCH_DEV_PCIE13 _PCH_DEV(PCIE_1, 4)
#define PCH_DEV_PCIE14 _PCH_DEV(PCIE_1, 5)
#define PCH_DEV_PCIE15 _PCH_DEV(PCIE_1, 6)
#define PCH_DEV_PCIE16 _PCH_DEV(PCIE_1, 7)
#define PCH_DEV_SLOT_PCIE_2 0x1b
#define PCH_DEVFN_PCIE17 _PCH_DEVFN(PCIE_2, 0)
#define PCH_DEVFN_PCIE18 _PCH_DEVFN(PCIE_2, 1)
#define PCH_DEVFN_PCIE19 _PCH_DEVFN(PCIE_2, 2)
#define PCH_DEVFN_PCIE20 _PCH_DEVFN(PCIE_2, 3)
#define PCH_DEVFN_PCIE21 _PCH_DEVFN(PCIE_2, 4)
#define PCH_DEVFN_PCIE22 _PCH_DEVFN(PCIE_2, 5)
#define PCH_DEVFN_PCIE23 _PCH_DEVFN(PCIE_2, 6)
#define PCH_DEVFN_PCIE24 _PCH_DEVFN(PCIE_2, 7)
#define PCH_DEV_PCIE17 _PCH_DEV(PCIE_2, 0)
#define PCH_DEV_PCIE18 _PCH_DEV(PCIE_2, 1)
#define PCH_DEV_PCIE19 _PCH_DEV(PCIE_2, 2)
#define PCH_DEV_PCIE20 _PCH_DEV(PCIE_2, 3)
#define PCH_DEV_PCIE21 _PCH_DEV(PCIE_2, 4)
#define PCH_DEV_PCIE22 _PCH_DEV(PCIE_2, 5)
#define PCH_DEV_PCIE23 _PCH_DEV(PCIE_2, 6)
#define PCH_DEV_PCIE24 _PCH_DEV(PCIE_2, 7)
#define PCH_DEV_SLOT_SIO5 0x1e #define PCH_DEV_SLOT_SIO5 0x1e
#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO5, 0) #define PCH_DEVFN_UART0 _PCH_DEVFN(SIO5, 0)