libpayload: xhci: Use Event Data TRBs for transfer event generation
The current XHCI code only sets IOC on the last TRB of a TD, and doesn't set ISP anywhere. On my Synopsys DesignWare3 controller, this won't generate an event at all when we have a short transfer that is not on the last TRB of a TD, resulting in event ring desync and everyone having a bad time. However, just setting ISP on other TRBs doesn't really make for a nice solution: we then need to do ugly special casing to fish out the spurious second transfer event you get for short packets, and we still need a way to figure out how many bytes were transferred. Since the Short Packet transfer event only reports untransferred bytes for the current TRB, we would have to manually walk the rest of the unprocessed TRB chain and add up the bytes. Check out U-Boot and the Linux kernel to see how complicated this looks in practice. Now what if we had a way to just tell the HC "I want an event at exactly *this* point in the TD, I want it to have the right completion code for the whole TD, and to contain the exact number of bytes written"? Enter the Event Data TRB: this little gizmo really does pretty much exactly what any sane XHCI driver would want, and I have no idea why it isn't used more often. It solves both the short packet event generation and counting the transferred bytes without requiring any special magic in software. Change-Id: Idab412d61edf30655ec69c80066bfffd80290403 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170980 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Kees Cook <keescook@chromium.org> (cherry picked from commit e512c8bcaa5b8e05cae3b9d04cd4947298de999d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6516 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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@ -551,6 +551,7 @@ xhci_enqueue_td(transfer_ring_t *const tr, const int ep, const size_t mps,
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trb->ptr_low = virt_to_phys(cur_start);
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TRB_SET(TL, trb, cur_length);
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TRB_SET(TDS, trb, packets);
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TRB_SET(CH, trb, 1);
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/* Check for first, data stage TRB */
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if (!trb_count && ep == 1) {
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@ -560,17 +561,19 @@ xhci_enqueue_td(transfer_ring_t *const tr, const int ep, const size_t mps,
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TRB_SET(TT, trb, TRB_NORMAL);
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}
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/* Check for last TRB */
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if (!length)
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TRB_SET(IOC, trb, 1);
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else
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TRB_SET(CH, trb, 1);
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xhci_enqueue_trb(tr);
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cur_start += cur_length;
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++trb_count;
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}
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trb = tr->cur;
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xhci_clear_trb(trb, tr->pcs);
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trb->ptr_low = virt_to_phys(trb); /* for easier debugging only */
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TRB_SET(TT, trb, TRB_EVENT_DATA);
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TRB_SET(IOC, trb, 1);
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xhci_enqueue_trb(tr);
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}
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static int
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@ -583,7 +586,7 @@ xhci_control(usbdev_t *const dev, const direction_t dir,
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transfer_ring_t *const tr = di->transfer_rings[1];
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const size_t off = (size_t)data & 0xffff;
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if ((off + dalen) > ((TRANSFER_RING_SIZE - 3) << 16)) {
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if ((off + dalen) > ((TRANSFER_RING_SIZE - 4) << 16)) {
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xhci_debug("Unsupported transfer size\n");
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return 1;
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}
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@ -670,7 +673,7 @@ xhci_bulk(endpoint_t *const ep,
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transfer_ring_t *const tr = di->transfer_rings[ep_id];
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const size_t off = (size_t)data & 0xffff;
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if ((off + size) > ((TRANSFER_RING_SIZE - 1) << 16)) {
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if ((off + size) > ((TRANSFER_RING_SIZE - 2) << 16)) {
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xhci_debug("Unsupported transfer size\n");
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return 1;
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}
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@ -65,7 +65,7 @@ enum { XHCI_FULL_SPEED = 1, XHCI_LOW_SPEED = 2, XHCI_HIGH_SPEED = 3, XHCI_SUPER_
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enum {
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TRB_NORMAL = 1,
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TRB_SETUP_STAGE = 2, TRB_DATA_STAGE = 3, TRB_STATUS_STAGE = 4,
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TRB_LINK = 6,
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TRB_LINK = 6, TRB_EVENT_DATA = 7,
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TRB_CMD_ENABLE_SLOT = 9, TRB_CMD_DISABLE_SLOT = 10, TRB_CMD_ADDRESS_DEV = 11,
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TRB_CMD_CONFIGURE_EP = 12, TRB_CMD_EVAL_CTX = 13, TRB_CMD_RESET_EP = 14,
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TRB_CMD_STOP_EP = 15, TRB_CMD_SET_TR_DQ = 16, TRB_CMD_NOOP = 23,
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@ -150,6 +150,7 @@ typedef struct {
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u8 adv;
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} event_ring_t;
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/* Never raise this above 256 to prevent transfer event length overflow! */
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#define TRANSFER_RING_SIZE 32
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typedef struct {
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trb_t *ring;
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