GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/braswell/ramstage.c: Add SoC stepping D-1 support 

No support for SoC D-1 stepping is available.

According to Intel doc #332095-015 stepping C-0 has revision
id 0x21 and D-1 revision ID 0x35.

Also correct the RID_C_STEPPING_START value for C-0.

BUG=none
TEST=Built, Intel Cherry Hill Rev F.

Change-Id: I29268f797f68aa4e3b6203e098485e0bd4a44fc4
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/27471
Reviewed-by: Wim Vervoorn
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Frans Hendriks 2018-07-13 09:52:04 +02:00 committed by Martin Roth
parent dc03528355
commit 83e7324969
2 changed files with 10 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/soc/intel/braswell/include/soc/lpc.h
View File

@ -3,6 +3,7 @@
* *
* Copyright (C) 2013 Google Inc. * Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corp. * Copyright (C) 2015 Intel Corp.
* Copyright (C) 2018 Eltan B.V.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -36,7 +37,8 @@
#define RID_A_STEPPING_START 1 #define RID_A_STEPPING_START 1
#define RID_B_STEPPING_START 5 #define RID_B_STEPPING_START 5
#define RID_C_STEPPING_START 0xe #define RID_C_STEPPING_START 0x21
#define RID_D_STEPPING_START 0x35
enum soc_stepping { enum soc_stepping {
STEP_A0, STEP_A0,
STEP_A1, STEP_A1,
@ -45,6 +47,7 @@ enum soc_stepping {
STEP_B2, STEP_B2,
STEP_B3, STEP_B3,
STEP_C0, STEP_C0,
STEP_D1,
}; };
/* Registers behind the RCBA_BASE_ADDRESS bar. */ /* Registers behind the RCBA_BASE_ADDRESS bar. */

8
src/soc/intel/braswell/ramstage.c
View File

@ -3,6 +3,7 @@
* *
* Copyright (C) 2013 Google Inc. * Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corp. * Copyright (C) 2015 Intel Corp.
* Copyright (C) 2018 Eltan B.V.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -73,7 +74,7 @@ static inline void fill_in_msr(msr_t *msr, int idx)
} }
static const char *const stepping_str[] = { static const char *const stepping_str[] = {
"A0", "A1", "B0", "B1", "B2", "B3", "C0" "A0", "A1", "B0", "B1", "B2", "B3", "C0", "D1"
}; };
static void fill_in_pattrs(void) static void fill_in_pattrs(void)
@ -86,7 +87,10 @@ static void fill_in_pattrs(void)
dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
attrs->revid = pci_read_config8(dev, REVID); attrs->revid = pci_read_config8(dev, REVID);
/* The revision to stepping IDs have two values per metal stepping. */ /* The revision to stepping IDs have two values per metal stepping. */
if (attrs->revid >= RID_C_STEPPING_START) { if (attrs->revid >= RID_D_STEPPING_START) {
attrs->stepping = (attrs->revid - RID_D_STEPPING_START) / 2;
attrs->stepping += STEP_D1;
} else if (attrs->revid >= RID_C_STEPPING_START) {
attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2; attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2;
attrs->stepping += STEP_C0; attrs->stepping += STEP_C0;
} else if (attrs->revid >= RID_B_STEPPING_START) { } else if (attrs->revid >= RID_B_STEPPING_START) {