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soc/intel/braswell: increase LPEA fw allocation to 2MiB 

Increase memory allocated for the LPEA firmware from 1MiB to 2MiB
to match Intel CHT reference code and fix Windows functionality.

Test: boot Windows on google/edgar, observe no error in Device Manager
for LPEA audio device due to BAR2 resource allocation.

Change-Id: I7cffcdd83a66a922c2454488c8650df03c9f5097
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Matt DeVillier 2018-01-21 16:37:24 -06:00 committed by Martin Roth
parent 7440cc881c
commit 83ef07a92a
2 changed files with 2 additions and 2 deletions
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2
src/soc/intel/braswell/acpi/lpe.asl
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@ -26,7 +26,7 @@ Device (LPEA)
{ {
Memory32Fixed (ReadWrite, 0, 0x00200000, BAR0) Memory32Fixed (ReadWrite, 0, 0x00200000, BAR0)
Memory32Fixed (ReadWrite, 0, 0x00001000, BAR1) Memory32Fixed (ReadWrite, 0, 0x00001000, BAR1)
Memory32Fixed (ReadWrite, 0, 0x00100000, BAR2) Memory32Fixed (ReadWrite, 0, 0x00200000, BAR2)
Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
{ {
LPE_DMA0_IRQ LPE_DMA0_IRQ

2
src/soc/intel/braswell/lpe.c
View File

@ -38,7 +38,7 @@
* address. Just take 1MiB @ 512MiB. * address. Just take 1MiB @ 512MiB.
*/ */
#define FIRMWARE_PHYS_BASE (512 << 20) #define FIRMWARE_PHYS_BASE (512 << 20)
#define FIRMWARE_PHYS_LENGTH (1 << 20) #define FIRMWARE_PHYS_LENGTH (2 << 20)
#define FIRMWARE_PCI_REG_BASE 0xa8 #define FIRMWARE_PCI_REG_BASE 0xa8
#define FIRMWARE_PCI_REG_LENGTH 0xac #define FIRMWARE_PCI_REG_LENGTH 0xac
#define FIRMWARE_REG_BASE_C0 0x144000 #define FIRMWARE_REG_BASE_C0 0x144000