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oprom: Fix for 64bit 

Change-Id: If4c1ab5ae33a64be3e7b14150d410edd291ee4ed
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10591
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Stefan Reinauer 2015-06-18 22:01:07 -07:00
parent 0e7b7bb6b3
commit 83fa169101
2 changed files with 2 additions and 2 deletions
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2
src/device/oprom/realmode/x86.c
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@ -188,7 +188,7 @@ static void setup_realmode_idt(void)
for (i = 0; i < 256; i++) { for (i = 0; i < 256; i++) {
idts[i].cs = 0; idts[i].cs = 0;
idts[i].offset = 0x1000 + (i * __idt_handler_size); idts[i].offset = 0x1000 + (i * __idt_handler_size);
write_idt_stub((void *)((u32 )idts[i].offset), i); write_idt_stub((void *)((uintptr_t)idts[i].offset), i);
} }
/* Many option ROMs use the hard coded interrupt entry points in the /* Many option ROMs use the hard coded interrupt entry points in the

2
src/device/pci_rom.c
View File

@ -57,7 +57,7 @@ struct rom_header *pci_rom_probe(struct device *dev)
printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n", printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n",
dev_path(dev), rom_header); dev_path(dev), rom_header);
} else { } else {
u32 rom_address; uintptr_t rom_address;
rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS);