soc/intel/tigerlake: Update interrupt info
Update interrupt header and interrupt mapping per Intel Silcon reference code. Need to match pci_irqs.asl with FSP setting which followed by PCH BIOS spec. Reference PCH BIOS spec#613495 https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSiliconPkg /IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/PeiItssPolicyLibVer2.c BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Iffc4efad4d0aa55fc0de88d7fe32c0356dbc3c60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38258 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wonkyu Kim
Patrick Georgi
parent
13471bc864
commit
8406179eff
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corp.
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* Copyright (C) 2020 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -17,115 +17,145 @@
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#include <soc/irq.h>
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Name (PICP, Package () {
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/* PCI Bridge */
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/* cAVS, SMBus, GbE, Nothpeak */
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Package(){0x001FFFFF, 0, 0, cAVS_INTA_IRQ },
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Package(){0x001FFFFF, 1, 0, SMBUS_INTB_IRQ },
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Package(){0x001FFFFF, 2, 0, GbE_INTC_IRQ },
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Package(){0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ },
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/* SerialIo and SCS */
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/* D31:HSA, SMBUS, TraceHUB */
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Package(){0x001FFFFF, 3, 0, HDA_IRQ },
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Package(){0x001FFFFF, 4, 0, SMBUS_IRQ },
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Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ },
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/* D30: UART0, UART1, SPI0, SPI1 */
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Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
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Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
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Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
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Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
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/* PCI Express Port 9-16 */
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/* D29: RP9 ~ RP12 */
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Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ },
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Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ },
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Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ },
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Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ },
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/* PCI Express Port 1-8 */
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/* D28: RP1 ~ RP8 */
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Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
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Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
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Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
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Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
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/* eMMC */
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Package(){0x001AFFFF, 0, 0, eMMC_IRQ },
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/* SerialIo */
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Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
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Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ },
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Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
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Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
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/* D25: I2C4, I2C5, UART2 */
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Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
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Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
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Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
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/* SATA controller */
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/* D23: SATA */
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Package(){0x0017FFFF, 0, 0, SATA_IRQ },
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/* CSME (HECI, IDE-R, Keyboard and Text redirection */
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/* D22: CSME */
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Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
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Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
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Package(){0x0016FFFF, 2, 0, IDER_IRQ },
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Package(){0x0016FFFF, 3, 0, KT_IRQ },
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/* SerialIo */
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Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
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Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
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/* D21: I2C0 ~ I2C3 */
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Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
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Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
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Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
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Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
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/* D20: xHCI, OTG, SRAM, CNVi WiFi */
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Package(){0x0014FFFF, 0, 0, XHCI_IRQ },
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Package(){0x0014FFFF, 1, 0, OTG_IRQ },
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Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ },
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Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ },
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/* Integrated Sensor Hub */
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Package(){0x0013FFFF, 0, 0, ISH_IRQ },
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/* Thermal */
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Package(){0x0012FFFF, 0, 0, THERMAL_IRQ },
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/* Host Bridge */
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/* Root Port D1F0 */
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Package(){0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ },
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Package(){0x0001FFFF, 1, 0, PEG_RP_INTB_IRQ },
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Package(){0x0001FFFF, 2, 0, PEG_RP_INTC_IRQ },
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Package(){0x0001FFFF, 3, 0, PEG_RP_INTD_IRQ },
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/* SA IGFX Device */
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Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
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/* SA Thermal Device */
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Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ },
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/* SA IPU Device */
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Package(){0x0005FFFF, 0, 0, IPU_IRQ },
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/* SA GNA Device */
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/* D20: xHCI, xDCI, SRAM, CNVI_WIFI */
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Package(){0x0014FFFF, 0, 0, xHCI_IRQ },
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Package(){0x0014FFFF, 1, 0, xDCI_IRQ },
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Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ },
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/* D19: SPI3 */
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Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ },
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/* D18: ISH, SPI2 */
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Package(){0x0012FFFF, 0, 0, ISH_IRQ },
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Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
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/* D16: CNVI_BT, TCH0, TCH1 */
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Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ },
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Package(){0x0010FFFF, 6, 0, THC0_IRQ },
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Package(){0x0010FFFF, 7, 0, THC1_IRQ },
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/* D13: xHCI, xDCI */
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Package(){0x000DFFFF, 0, 0, xHCI_IRQ },
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Package(){0x000DFFFF, 1, 0, xDCI_IRQ },
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/* D8: GNA */
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Package(){0x0008FFFF, 0, 0, GNA_IRQ },
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/* D7: TBT PCIe */
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Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ },
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Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ },
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Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ },
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Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ },
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/* D6: PEG60 */
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Package(){0x0006FFFF, 0, 0, PEG_IRQ },
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/* D5: IPU Device */
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Package(){0x0005FFFF, 0, 0, IPU_IRQ },
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/* D4: Thermal Device */
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Package(){0x0004FFFF, 0, 0, THERMAL_IRQ },
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/* D2: IGFX */
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Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
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})
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Name (PICN, Package () {
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/* D31: cAVS, SMBus, GbE, Nothpeak */
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Package () { 0x001FFFFF, 0, 0, 11 },
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Package () { 0x001FFFFF, 1, 0, 10 },
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Package () { 0x001FFFFF, 2, 0, 11 },
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/* D31:HSA, SMBUS, TraceHUB*/
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Package () { 0x001FFFFF, 3, 0, 11 },
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/* D30: Can't use PIC*/
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/* D29: PCI Express Port 9-16 */
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Package () { 0x001FFFFF, 4, 0, 11 },
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Package () { 0x001FFFFF, 7, 0, 11 },
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/* D30: UART0, UART1, SPI0, SPI1 */
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Package () { 0x001EFFFF, 0, 0, 11 },
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Package () { 0x001EFFFF, 1, 0, 10 },
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Package () { 0x001EFFFF, 2, 0, 11 },
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Package () { 0x001EFFFF, 3, 0, 11 },
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/* D29: RP9 ~ RP12 */
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Package () { 0x001DFFFF, 0, 0, 11 },
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Package () { 0x001DFFFF, 1, 0, 10 },
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Package () { 0x001DFFFF, 2, 0, 11 },
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Package () { 0x001DFFFF, 3, 0, 11 },
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/* D28: PCI Express Port 1-8 */
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/* D28: RP1 ~ RP8 */
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Package () { 0x001CFFFF, 0, 0, 11 },
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Package () { 0x001CFFFF, 1, 0, 10 },
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Package () { 0x001CFFFF, 2, 0, 11 },
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Package () { 0x001CFFFF, 3, 0, 11 },
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/* D26: Can't use PIC*/
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/* D25: Can't use PIC*/
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/* D23: SATA controller */
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Package () { 0x001CFFFF, 4, 0, 11 },
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Package () { 0x001CFFFF, 5, 0, 10 },
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Package () { 0x001CFFFF, 6, 0, 11 },
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Package () { 0x001CFFFF, 7, 0, 11 },
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/* D25: I2C4, I2C5, UART2 */
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Package(){0x0019FFFF, 0, 0, 11 },
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Package(){0x0019FFFF, 1, 0, 10 },
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Package(){0x0019FFFF, 2, 0, 11 },
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/* D23: SATA */
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Package () { 0x0017FFFF, 0, 0, 11 },
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/* D22: CSME (HECI, IDE-R, KT redirection */
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Package () { 0x0016FFFF, 0, 0, 11 },
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Package () { 0x0016FFFF, 1, 0, 10 },
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Package () { 0x0016FFFF, 2, 0, 11 },
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Package () { 0x0016FFFF, 3, 0, 11 },
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/* D20: xHCI, OTG, SRAM, CNVi WiFi */
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Package () { 0x0014FFFF, 0, 0, 11 },
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Package () { 0x0014FFFF, 1, 0, 10 },
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Package () { 0x0014FFFF, 2, 0, 11 },
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Package () { 0x0014FFFF, 3, 0, 11 },
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/* D18: Can't use PIC*/
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/* P.E.G. Root Port D1F0 */
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Package () { 0x0001FFFF, 0, 0, 11 },
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Package () { 0x0001FFFF, 1, 0, 10 },
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Package () { 0x0001FFFF, 2, 0, 11 },
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Package () { 0x0001FFFF, 3, 0, 11 },
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/* SA IGFX Device */
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Package () { 0x0002FFFF, 0, 0, 11 },
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/* SA Thermal Device */
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Package () { 0x0004FFFF, 0, 0, 11 },
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/* SA IPU Device */
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Package () { 0x0005FFFF, 0, 0, 11 },
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/* SA GNA Device */
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Package () { 0x0008FFFF, 0, 0, 11 },
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/* D22: CSME */
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Package(){0x0016FFFF, 0, 0, 11 },
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Package(){0x0016FFFF, 1, 0, 10 },
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Package(){0x0016FFFF, 4, 0, 11 },
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Package(){0x0016FFFF, 5, 0, 11 },
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/* D21: I2C0 ~ I2C3 */
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Package(){0x0015FFFF, 0, 0, 11 },
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Package(){0x0015FFFF, 1, 0, 10 },
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Package(){0x0015FFFF, 2, 0, 11 },
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Package(){0x0015FFFF, 3, 0, 11 },
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/* D19: SPI3 */
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Package(){0x0013FFFF, 0, 0, 11 },
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/* D18: ISH, SPI2 */
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Package(){0x0012FFFF, 0, 0, 11 },
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Package(){0x0012FFFF, 6, 0, 11 },,
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/* D16: CNVI_BT, TCH0, TCH1 */
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Package(){0x0010FFFF, 2, 0, 11 },
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Package(){0x0010FFFF, 6, 0, 11 },
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Package(){0x0010FFFF, 7, 0, 10 },
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/* D13: xHCI, xDCI */
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Package(){0x000DFFFF, 0, 0, 11 },
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Package(){0x000DFFFF, 1, 0, 10 },
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/* D8: GNA */
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Package(){0x0008FFFF, 0, 0, 11 },
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/* D7: TBT PCIe */
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Package(){0x0007FFFF, 0, 0, 11 },
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Package(){0x0007FFFF, 1, 0, 10 },
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Package(){0x0007FFFF, 2, 0, 11 },
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Package(){0x0007FFFF, 3, 0, 11 },
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/* D6: PEG60 */
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Package(){0x0006FFFF, 0, 0, 11 },
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/* D5: IPU Device */
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Package(){0x0005FFFF, 0, 0, 11 },
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/* D4: Thermal Device */
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Package(){0x0004FFFF, 0, 0, 11 },
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/* D2: IGFX */
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Package(){0x0002FFFF, 0, 0, 11 },
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})
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Method (_PRT)
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Intel Corporation.
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* Copyright (C) 2020 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -16,91 +16,69 @@
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#ifndef _SOC_IRQ_H_
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#define _SOC_IRQ_H_
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#define GPIO_IRQ14 14
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#define GPIO_IRQ15 15
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#define GPIO_IRQ14 14
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#define GPIO_IRQ15 15
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#define PCH_IRQ10 10
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#define PCH_IRQ11 11
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#define PCH_IRQ10 10
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#define PCH_IRQ11 11
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#define SCI_IRQ9 9
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#define SCI_IRQ10 10
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#define SCI_IRQ11 11
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#define SCI_IRQ20 20
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#define SCI_IRQ21 21
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#define SCI_IRQ22 22
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#define SCI_IRQ23 23
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#define LPSS_I2C0_IRQ 27
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#define LPSS_I2C1_IRQ 28
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#define LPSS_I2C2_IRQ 29
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#define LPSS_I2C3_IRQ 30
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#define LPSS_I2C4_IRQ 31
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#define LPSS_I2C5_IRQ 32
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#define LPSS_SPI0_IRQ 36
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#define LPSS_SPI1_IRQ 37
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#define LPSS_SPI2_IRQ 18
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#define LPSS_SPI3_IRQ 23
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#define LPSS_UART0_IRQ 34
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#define LPSS_UART1_IRQ 35
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#define LPSS_UART2_IRQ 33
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#define TCO_IRQ9 9
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#define TCO_IRQ10 10
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#define TCO_IRQ11 11
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#define TCO_IRQ20 20
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#define TCO_IRQ21 21
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#define TCO_IRQ22 22
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#define TCO_IRQ23 23
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#define HDA_IRQ 16
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#define SMBUS_IRQ 16
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#define TRACEHUB_IRQ 16
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#define LPSS_I2C0_IRQ 16
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#define LPSS_I2C1_IRQ 17
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#define LPSS_I2C2_IRQ 18
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#define LPSS_I2C3_IRQ 19
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#define LPSS_I2C4_IRQ 32
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#define LPSS_I2C5_IRQ 33
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#define LPSS_SPI0_IRQ 22
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#define LPSS_SPI1_IRQ 23
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#define LPSS_SPI2_IRQ 24
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#define LPSS_UART0_IRQ 20
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#define LPSS_UART1_IRQ 21
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#define LPSS_UART2_IRQ 34
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#define SDIO_IRQ 22
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#define PCIE_1_IRQ 16
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#define PCIE_2_IRQ 17
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#define PCIE_3_IRQ 18
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#define PCIE_4_IRQ 19
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#define PCIE_5_IRQ 16
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#define PCIE_6_IRQ 17
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#define PCIE_7_IRQ 18
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#define PCIE_8_IRQ 19
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#define PCIE_9_IRQ 16
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#define PCIE_10_IRQ 17
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#define PCIE_11_IRQ 18
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#define PCIE_12_IRQ 19
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#define cAVS_INTA_IRQ 16
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#define SMBUS_INTA_IRQ 16
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#define SMBUS_INTB_IRQ 17
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#define GbE_INTA_IRQ 16
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#define GbE_INTC_IRQ 18
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#define TRACE_HUB_INTA_IRQ 16
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#define TRACE_HUB_INTD_IRQ 19
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#define SATA_IRQ 16
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#define eMMC_IRQ 16
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#define SD_IRQ 19
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#define xHCI_IRQ 16
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#define xDCI_IRQ 17
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#define CNVI_WIFI_IRQ 16
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#define PCIE_1_IRQ 16
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#define PCIE_2_IRQ 17
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#define PCIE_3_IRQ 18
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#define PCIE_4_IRQ 19
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#define PCIE_5_IRQ 16
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#define PCIE_6_IRQ 17
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#define PCIE_7_IRQ 18
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#define PCIE_8_IRQ 19
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#define PCIE_9_IRQ 16
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#define PCIE_10_IRQ 17
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#define PCIE_11_IRQ 18
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#define PCIE_12_IRQ 19
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#define CNVI_BT_IRQ 18
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#define SATA_IRQ 16
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#define THC0_IRQ 16
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#define THC1_IRQ 17
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#define HECI_1_IRQ 16
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#define HECI_2_IRQ 17
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#define IDER_IRQ 18
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#define KT_IRQ 19
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#define HECI_3_IRQ 16
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#define ISH_IRQ 16
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#define XHCI_IRQ 16
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#define OTG_IRQ 17
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#define PMC_SRAM_IRQ 18
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#define THERMAL_IRQ 16
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#define CNViWIFI_IRQ 19
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#define UFS_IRQ 16
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#define CIO_INTA_IRQ 16
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#define CIO_INTD_IRQ 19
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#define ISH_IRQ 20
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#define TBT_PCIe0_IRQ 16
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#define TBT_PCIe1_IRQ 17
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#define TBT_PCIe2_IRQ 18
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#define TBT_PCIe3_IRQ 19
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#define PEG_RP_INTA_IRQ 16
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#define PEG_RP_INTB_IRQ 17
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#define PEG_RP_INTC_IRQ 18
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#define PEG_RP_INTD_IRQ 19
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#define HECI_1_IRQ 16
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#define HECI_2_IRQ 17
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#define HECI_3_IRQ 16
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#define HECI_4_IRQ 19
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#define IGFX_IRQ 16
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#define SA_THERMAL_IRQ 16
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#define IPU_IRQ 16
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#define GNA_IRQ 16
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#define PEG_IRQ 16
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#define IGFX_IRQ 16
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#define THERMAL_IRQ 16
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#define IPU_IRQ 16
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#define GNA_IRQ 16
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#endif /* _SOC_IRQ_H_ */
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