soc/intel/tigerlake: Update interrupt info

Update interrupt header and interrupt mapping per Intel Silcon reference code.
Need to match pci_irqs.asl with FSP setting which followed by PCH BIOS spec.

Reference
PCH BIOS spec#613495
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSiliconPkg
/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/PeiItssPolicyLibVer2.c

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iffc4efad4d0aa55fc0de88d7fe32c0356dbc3c60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38258
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/tigerlake/acpi/pci_irqs.asl

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2019 Intel Corp.
+ * Copyright (C) 2020 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,115 +17,145 @@
 #include <soc/irq.h>
 
 Name (PICP, Package () {
-	/* PCI Bridge */
-	/* cAVS, SMBus, GbE, Nothpeak */
-	Package(){0x001FFFFF, 0, 0, cAVS_INTA_IRQ },
-	Package(){0x001FFFFF, 1, 0, SMBUS_INTB_IRQ },
-	Package(){0x001FFFFF, 2, 0, GbE_INTC_IRQ },
-	Package(){0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ },
-	/* SerialIo and SCS */
+	/* D31:HSA, SMBUS, TraceHUB */
+	Package(){0x001FFFFF, 3, 0, HDA_IRQ },
+	Package(){0x001FFFFF, 4, 0, SMBUS_IRQ },
+	Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ },
+	/* D30: UART0, UART1, SPI0, SPI1 */
 	Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
 	Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
 	Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
 	Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
-	/* PCI Express Port 9-16 */
+	/* D29: RP9 ~ RP12 */
 	Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ },
 	Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ },
 	Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ },
 	Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ },
-	/* PCI Express Port 1-8 */
+	/* D28: RP1 ~ RP8 */
 	Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
 	Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
 	Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
 	Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
-	/* eMMC */
-	Package(){0x001AFFFF, 0, 0, eMMC_IRQ },
-	/* SerialIo */
+	Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
+	Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ },
+	Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
+	Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
+	/* D25: I2C4, I2C5, UART2 */
 	Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
 	Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
 	Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
-	/* SATA controller */
+	/* D23: SATA */
 	Package(){0x0017FFFF, 0, 0, SATA_IRQ },
-	/* CSME (HECI, IDE-R, Keyboard and Text redirection */
+	/* D22: CSME */
 	Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
 	Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
-	Package(){0x0016FFFF, 2, 0, IDER_IRQ },
-	Package(){0x0016FFFF, 3, 0, KT_IRQ },
-	/* SerialIo */
+	Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
+	Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
+	/* D21: I2C0 ~ I2C3 */
 	Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
 	Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
 	Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
 	Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
-	/* D20: xHCI, OTG, SRAM, CNVi WiFi */
-	Package(){0x0014FFFF, 0, 0, XHCI_IRQ },
-	Package(){0x0014FFFF, 1, 0, OTG_IRQ },
-	Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ },
-	Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ },
-	/* Integrated Sensor Hub */
-	Package(){0x0013FFFF, 0, 0, ISH_IRQ },
-	/* Thermal */
-	Package(){0x0012FFFF, 0, 0, THERMAL_IRQ },
-	/* Host Bridge */
-	/* Root Port D1F0 */
-	Package(){0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ },
-	Package(){0x0001FFFF, 1, 0, PEG_RP_INTB_IRQ },
-	Package(){0x0001FFFF, 2, 0, PEG_RP_INTC_IRQ },
-	Package(){0x0001FFFF, 3, 0, PEG_RP_INTD_IRQ },
-	/* SA IGFX Device */
-	Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
-	/* SA Thermal Device */
-	Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ },
-	/* SA IPU Device */
-	Package(){0x0005FFFF, 0, 0, IPU_IRQ },
-	/* SA GNA Device */
+	/* D20: xHCI, xDCI, SRAM, CNVI_WIFI */
+	Package(){0x0014FFFF, 0, 0, xHCI_IRQ },
+	Package(){0x0014FFFF, 1, 0, xDCI_IRQ },
+	Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ },
+	/* D19: SPI3 */
+	Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ },
+	/* D18: ISH, SPI2 */
+	Package(){0x0012FFFF, 0, 0, ISH_IRQ },
+	Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
+	/* D16: CNVI_BT, TCH0, TCH1 */
+	Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ },
+	Package(){0x0010FFFF, 6, 0, THC0_IRQ },
+	Package(){0x0010FFFF, 7, 0, THC1_IRQ },
+	/* D13: xHCI, xDCI */
+	Package(){0x000DFFFF, 0, 0, xHCI_IRQ },
+	Package(){0x000DFFFF, 1, 0, xDCI_IRQ },
+	/* D8: GNA */
 	Package(){0x0008FFFF, 0, 0, GNA_IRQ },
+	/* D7: TBT PCIe */
+	Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ },
+	Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ },
+	Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ },
+	Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ },
+	/* D6: PEG60 */
+	Package(){0x0006FFFF, 0, 0, PEG_IRQ },
+	/* D5: IPU Device */
+	Package(){0x0005FFFF, 0, 0, IPU_IRQ },
+	/* D4:  Thermal Device */
+	Package(){0x0004FFFF, 0, 0, THERMAL_IRQ },
+	/* D2: IGFX */
+	Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
 })
 
 Name (PICN, Package () {
-	/* D31: cAVS, SMBus, GbE, Nothpeak */
-	Package () { 0x001FFFFF, 0, 0, 11 },
-	Package () { 0x001FFFFF, 1, 0, 10 },
-	Package () { 0x001FFFFF, 2, 0, 11 },
+	/* D31:HSA, SMBUS, TraceHUB*/
 	Package () { 0x001FFFFF, 3, 0, 11 },
-	/* D30: Can't use PIC*/
-	/* D29: PCI Express Port 9-16 */
+	Package () { 0x001FFFFF, 4, 0, 11 },
+	Package () { 0x001FFFFF, 7, 0, 11 },
+	/* D30: UART0, UART1, SPI0, SPI1 */
+	Package () { 0x001EFFFF, 0, 0, 11 },
+	Package () { 0x001EFFFF, 1, 0, 10 },
+	Package () { 0x001EFFFF, 2, 0, 11 },
+	Package () { 0x001EFFFF, 3, 0, 11 },
+	/* D29: RP9 ~ RP12 */
 	Package () { 0x001DFFFF, 0, 0, 11 },
 	Package () { 0x001DFFFF, 1, 0, 10 },
 	Package () { 0x001DFFFF, 2, 0, 11 },
 	Package () { 0x001DFFFF, 3, 0, 11 },
-	/* D28: PCI Express Port 1-8 */
+	/* D28: RP1 ~ RP8 */
 	Package () { 0x001CFFFF, 0, 0, 11 },
 	Package () { 0x001CFFFF, 1, 0, 10 },
 	Package () { 0x001CFFFF, 2, 0, 11 },
 	Package () { 0x001CFFFF, 3, 0, 11 },
-	/* D26: Can't use PIC*/
-	/* D25: Can't use PIC*/
-	/* D23: SATA controller */
+	Package () { 0x001CFFFF, 4, 0, 11 },
+	Package () { 0x001CFFFF, 5, 0, 10 },
+	Package () { 0x001CFFFF, 6, 0, 11 },
+	Package () { 0x001CFFFF, 7, 0, 11 },
+	/* D25: I2C4, I2C5, UART2 */
+	Package(){0x0019FFFF, 0, 0, 11 },
+	Package(){0x0019FFFF, 1, 0, 10 },
+	Package(){0x0019FFFF, 2, 0, 11 },
+	/* D23: SATA */
 	Package () { 0x0017FFFF, 0, 0, 11 },
-	/* D22: CSME (HECI, IDE-R, KT redirection */
-	Package () { 0x0016FFFF, 0, 0, 11 },
-	Package () { 0x0016FFFF, 1, 0, 10 },
-	Package () { 0x0016FFFF, 2, 0, 11 },
-	Package () { 0x0016FFFF, 3, 0, 11 },
-	/* D20: xHCI, OTG, SRAM, CNVi WiFi */
-	Package () { 0x0014FFFF, 0, 0, 11 },
-	Package () { 0x0014FFFF, 1, 0, 10 },
-	Package () { 0x0014FFFF, 2, 0, 11 },
-	Package () { 0x0014FFFF, 3, 0, 11 },
-	/* D18: Can't use PIC*/
-	/* P.E.G. Root Port D1F0 */
-	Package () { 0x0001FFFF, 0, 0, 11 },
-	Package () { 0x0001FFFF, 1, 0, 10 },
-	Package () { 0x0001FFFF, 2, 0, 11 },
-	Package () { 0x0001FFFF, 3, 0, 11 },
-	/* SA IGFX Device */
-	Package () { 0x0002FFFF, 0, 0, 11 },
-	/* SA Thermal Device */
-	Package () { 0x0004FFFF, 0, 0, 11 },
-	/* SA IPU Device */
-	Package () { 0x0005FFFF, 0, 0, 11 },
-	/* SA GNA Device */
-	Package () { 0x0008FFFF, 0, 0, 11 },
+	/* D22: CSME */
+	Package(){0x0016FFFF, 0, 0, 11 },
+	Package(){0x0016FFFF, 1, 0, 10 },
+	Package(){0x0016FFFF, 4, 0, 11 },
+	Package(){0x0016FFFF, 5, 0, 11 },
+	/* D21: I2C0 ~ I2C3 */
+	Package(){0x0015FFFF, 0, 0, 11 },
+	Package(){0x0015FFFF, 1, 0, 10 },
+	Package(){0x0015FFFF, 2, 0, 11 },
+	Package(){0x0015FFFF, 3, 0, 11 },
+	/* D19: SPI3 */
+	Package(){0x0013FFFF, 0, 0, 11 },
+	/* D18: ISH, SPI2 */
+	Package(){0x0012FFFF, 0, 0, 11 },
+	Package(){0x0012FFFF, 6, 0, 11 },,
+	/* D16: CNVI_BT, TCH0, TCH1 */
+	Package(){0x0010FFFF, 2, 0, 11 },
+	Package(){0x0010FFFF, 6, 0, 11 },
+	Package(){0x0010FFFF, 7, 0, 10 },
+	/* D13: xHCI, xDCI */
+	Package(){0x000DFFFF, 0, 0, 11 },
+	Package(){0x000DFFFF, 1, 0, 10 },
+	/* D8: GNA */
+	Package(){0x0008FFFF, 0, 0, 11 },
+	/* D7: TBT PCIe */
+	Package(){0x0007FFFF, 0, 0, 11 },
+	Package(){0x0007FFFF, 1, 0, 10 },
+	Package(){0x0007FFFF, 2, 0, 11 },
+	Package(){0x0007FFFF, 3, 0, 11 },
+	/* D6: PEG60 */
+	Package(){0x0006FFFF, 0, 0, 11 },
+	/* D5: IPU Device */
+	Package(){0x0005FFFF, 0, 0, 11 },
+	/* D4:  Thermal Device */
+	Package(){0x0004FFFF, 0, 0, 11 },
+	/* D2: IGFX */
+	Package(){0x0002FFFF, 0, 0, 11 },
 })
 
 Method (_PRT)

src/soc/intel/tigerlake/include/soc/irq.h

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2018 Intel Corporation.
+ * Copyright (C) 2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -22,46 +22,23 @@
 #define PCH_IRQ10	10
 #define PCH_IRQ11	11
 
-#define SCI_IRQ9 9
-#define SCI_IRQ10 10
-#define SCI_IRQ11 11
-#define SCI_IRQ20 20
-#define SCI_IRQ21 21
-#define SCI_IRQ22 22
-#define SCI_IRQ23 23
+#define LPSS_I2C0_IRQ	27
+#define LPSS_I2C1_IRQ	28
+#define LPSS_I2C2_IRQ	29
+#define LPSS_I2C3_IRQ	30
+#define LPSS_I2C4_IRQ	31
+#define LPSS_I2C5_IRQ	32
+#define LPSS_SPI0_IRQ	36
+#define LPSS_SPI1_IRQ	37
+#define LPSS_SPI2_IRQ	18
+#define LPSS_SPI3_IRQ	23
+#define LPSS_UART0_IRQ	34
+#define LPSS_UART1_IRQ	35
+#define LPSS_UART2_IRQ	33
 
-#define TCO_IRQ9 9
-#define TCO_IRQ10 10
-#define TCO_IRQ11 11
-#define TCO_IRQ20 20
-#define TCO_IRQ21 21
-#define TCO_IRQ22 22
-#define TCO_IRQ23 23
-
-#define LPSS_I2C0_IRQ 16
-#define LPSS_I2C1_IRQ 17
-#define LPSS_I2C2_IRQ 18
-#define LPSS_I2C3_IRQ 19
-#define LPSS_I2C4_IRQ 32
-#define LPSS_I2C5_IRQ 33
-#define LPSS_SPI0_IRQ 22
-#define LPSS_SPI1_IRQ 23
-#define LPSS_SPI2_IRQ 24
-#define LPSS_UART0_IRQ 20
-#define LPSS_UART1_IRQ 21
-#define LPSS_UART2_IRQ 34
-#define SDIO_IRQ 22
-
-#define cAVS_INTA_IRQ 16
-#define SMBUS_INTA_IRQ 16
-#define SMBUS_INTB_IRQ 17
-#define GbE_INTA_IRQ 16
-#define GbE_INTC_IRQ 18
-#define TRACE_HUB_INTA_IRQ 16
-#define TRACE_HUB_INTD_IRQ 19
-
-#define eMMC_IRQ 16
-#define SD_IRQ 19
+#define HDA_IRQ		16
+#define SMBUS_IRQ	16
+#define TRACEHUB_IRQ	16
 
 #define PCIE_1_IRQ	16
 #define PCIE_2_IRQ	17
@@ -78,29 +55,30 @@
 
 #define SATA_IRQ	16
 
+#define xHCI_IRQ	16
+#define xDCI_IRQ	17
+#define CNVI_WIFI_IRQ	16
+
+#define CNVI_BT_IRQ	18
+
+#define THC0_IRQ	16
+#define THC1_IRQ	17
+
+#define ISH_IRQ		16
+
+#define TBT_PCIe0_IRQ	16
+#define TBT_PCIe1_IRQ	17
+#define TBT_PCIe2_IRQ	18
+#define TBT_PCIe3_IRQ	19
+
 #define HECI_1_IRQ	16
 #define HECI_2_IRQ	17
-#define IDER_IRQ 18
-#define KT_IRQ 19
 #define HECI_3_IRQ	16
+#define HECI_4_IRQ	19
 
-#define XHCI_IRQ 16
-#define OTG_IRQ 17
-#define PMC_SRAM_IRQ 18
-#define THERMAL_IRQ 16
-#define CNViWIFI_IRQ 19
-#define UFS_IRQ 16
-#define CIO_INTA_IRQ 16
-#define CIO_INTD_IRQ 19
-#define ISH_IRQ 20
-
-#define PEG_RP_INTA_IRQ 16
-#define PEG_RP_INTB_IRQ 17
-#define PEG_RP_INTC_IRQ 18
-#define PEG_RP_INTD_IRQ 19
-
+#define PEG_IRQ		16
 #define IGFX_IRQ	16
-#define SA_THERMAL_IRQ 16
+#define THERMAL_IRQ	16
 #define IPU_IRQ		16
 #define GNA_IRQ		16
 #endif /* _SOC_IRQ_H_ */