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soc/intel/cnl: Sync CONFIG_LPSS_UART_FOR_CONSOLE with FSP 

We got rid of the dangerous reconfiguration of arbitrary pads in
coreboot, but FSP still overrode that. Make sure that it doesn't
enable a UART for debug output when it isn't configured in core-
boot.

This, again, shows how dangerous it is to leave any FSP UPD at
its binary default.

Change-Id: I7280a80f71ddddbe78352eb696e6f5844d2df0b2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Nico Huber 2019-06-28 16:12:47 +02:00 committed by Nico Huber
parent 0c4ed4bd7e
commit 8417485f95
1 changed files with 3 additions and 0 deletions
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3
src/soc/intel/cannonlake/fsp_params.c
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@ -285,6 +285,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Set Debug serial port */
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
#if !CONFIG(SOC_INTEL_COMETLAKE)
params->SerialIoEnableDebugUartAfterPost = CONFIG_INTEL_LPSS_UART_FOR_CONSOLE;
#endif
/* Enable CNVi Wifi if enabled in device tree */
dev = pcidev_path_on_root(PCH_DEVFN_CNViWIFI);