lib/fit_payload: Add coreboot tables support for FDT.
Copy code of depthcharge boot/coreboot.c and adapt it. Tested on Cavium CN8100 EVB SFF, /sys/firmware/log is readable and prints the log. Change-Id: Ib714a021a24f51407558f484cd97aa58ecd43977 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/28104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
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@ -111,6 +111,8 @@ void cbmem_fail_resume(void);
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/* Ramstage only functions. */
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/* Add the cbmem memory used to the memory map at boot. */
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void cbmem_add_bootmem(void);
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/* Return the cbmem memory used */
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void cbmem_get_region(void **baseptr, size_t *size);
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void cbmem_list(void);
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void cbmem_add_records_to_cbtable(struct lb_header *header);
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@ -29,6 +29,7 @@
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#include <commonlib/compression.h>
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#include <lib.h>
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#include <fit_payload.h>
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#include <boardid.h>
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/* Pack the device_tree and place it at given position. */
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static void pack_fdt(struct region *fdt, struct device_tree *dt)
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@ -96,6 +97,67 @@ static bool extract(struct region *region, struct fit_image_node *node)
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return false;
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}
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/**
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* Add coreboot tables, CBMEM information and optional board specific strapping
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* IDs to the device tree loaded via FIT.
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*/
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static void add_cb_fdt_data(struct device_tree *tree)
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{
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u32 addr_cells = 1, size_cells = 1;
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u64 reg_addrs[2], reg_sizes[2];
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void *baseptr = NULL;
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size_t size = 0;
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static const char *firmware_path[] = {"firmware", NULL};
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struct device_tree_node *firmware_node = dt_find_node(tree->root,
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firmware_path, &addr_cells, &size_cells, 1);
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/* Need to add 'ranges' to the intermediate node to make 'reg' work. */
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dt_add_bin_prop(firmware_node, "ranges", NULL, 0);
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static const char *coreboot_path[] = {"coreboot", NULL};
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struct device_tree_node *coreboot_node = dt_find_node(firmware_node,
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coreboot_path, &addr_cells, &size_cells, 1);
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dt_add_string_prop(coreboot_node, "compatible", strdup("coreboot"));
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/* Fetch CB tables from cbmem */
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void *cbtable = cbmem_find(CBMEM_ID_CBTABLE);
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if (!cbtable) {
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printk(BIOS_WARNING, "FIT: No coreboot table found!\n");
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return;
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}
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/* First 'reg' address range is the coreboot table. */
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const struct lb_header *header = cbtable;
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reg_addrs[0] = (uintptr_t)header;
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reg_sizes[0] = header->header_bytes + header->table_bytes;
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/* Second is the CBMEM area (which usually includes the coreboot
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table). */
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cbmem_get_region(&baseptr, &size);
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if (!baseptr || size == 0) {
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printk(BIOS_WARNING, "FIT: CBMEM pointer/size not found!\n");
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return;
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}
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reg_addrs[1] = (uintptr_t)baseptr;
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reg_sizes[1] = size;
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dt_add_reg_prop(coreboot_node, reg_addrs, reg_sizes, 2, addr_cells,
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size_cells);
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/* Expose board ID, SKU ID, and RAM code to payload.*/
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if (board_id() != UNDEFINED_STRAPPING_ID)
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dt_add_u32_prop(coreboot_node, "board-id", board_id());
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if (sku_id() != UNDEFINED_STRAPPING_ID)
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dt_add_u32_prop(coreboot_node, "sku-id", sku_id());
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if (ram_code() != UNDEFINED_STRAPPING_ID)
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dt_add_u32_prop(coreboot_node, "ram-code", ram_code());
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}
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/*
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* Parse the uImage FIT, choose a configuration and extract images.
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*/
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@ -131,6 +193,9 @@ void fit_payload(struct prog *payload)
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dt_apply_fixups(dt);
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/* Insert coreboot specific information */
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add_cb_fdt_data(dt);
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/* Update device_tree */
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#if defined(CONFIG_LINUX_COMMAND_LINE)
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fit_update_chosen(dt, (char *)CONFIG_LINUX_COMMAND_LINE);
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@ -299,10 +299,15 @@ void cbmem_add_bootmem(void)
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void *baseptr = NULL;
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size_t size = 0;
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imd_region_used(cbmem_get_imd(), &baseptr, &size);
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cbmem_get_region(&baseptr, &size);
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bootmem_add_range((uintptr_t)baseptr, size, BM_MEM_TABLE);
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}
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void cbmem_get_region(void **baseptr, size_t *size)
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{
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imd_region_used(cbmem_get_imd(), baseptr, size);
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}
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#if ENV_RAMSTAGE || (IS_ENABLED(CONFIG_EARLY_CBMEM_LIST) \
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&& (ENV_POSTCAR || ENV_ROMSTAGE))
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/*
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