lib/fit_payload: Add coreboot tables support for FDT.

Copy code of depthcharge boot/coreboot.c and adapt it.

Tested on Cavium CN8100 EVB SFF, /sys/firmware/log is readable
and prints the log.

Change-Id: Ib714a021a24f51407558f484cd97aa58ecd43977
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/28104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Philipp Deppenwiese 2018-08-16 00:31:26 +02:00 committed by Patrick Rudolph
parent fa1a07bf50
commit 84258db5d5
3 changed files with 73 additions and 1 deletions

View File

@ -111,6 +111,8 @@ void cbmem_fail_resume(void);
/* Ramstage only functions. */
/* Add the cbmem memory used to the memory map at boot. */
void cbmem_add_bootmem(void);
/* Return the cbmem memory used */
void cbmem_get_region(void **baseptr, size_t *size);
void cbmem_list(void);
void cbmem_add_records_to_cbtable(struct lb_header *header);

View File

@ -29,6 +29,7 @@
#include <commonlib/compression.h>
#include <lib.h>
#include <fit_payload.h>
#include <boardid.h>
/* Pack the device_tree and place it at given position. */
static void pack_fdt(struct region *fdt, struct device_tree *dt)
@ -96,6 +97,67 @@ static bool extract(struct region *region, struct fit_image_node *node)
return false;
}
/**
* Add coreboot tables, CBMEM information and optional board specific strapping
* IDs to the device tree loaded via FIT.
*/
static void add_cb_fdt_data(struct device_tree *tree)
{
u32 addr_cells = 1, size_cells = 1;
u64 reg_addrs[2], reg_sizes[2];
void *baseptr = NULL;
size_t size = 0;
static const char *firmware_path[] = {"firmware", NULL};
struct device_tree_node *firmware_node = dt_find_node(tree->root,
firmware_path, &addr_cells, &size_cells, 1);
/* Need to add 'ranges' to the intermediate node to make 'reg' work. */
dt_add_bin_prop(firmware_node, "ranges", NULL, 0);
static const char *coreboot_path[] = {"coreboot", NULL};
struct device_tree_node *coreboot_node = dt_find_node(firmware_node,
coreboot_path, &addr_cells, &size_cells, 1);
dt_add_string_prop(coreboot_node, "compatible", strdup("coreboot"));
/* Fetch CB tables from cbmem */
void *cbtable = cbmem_find(CBMEM_ID_CBTABLE);
if (!cbtable) {
printk(BIOS_WARNING, "FIT: No coreboot table found!\n");
return;
}
/* First 'reg' address range is the coreboot table. */
const struct lb_header *header = cbtable;
reg_addrs[0] = (uintptr_t)header;
reg_sizes[0] = header->header_bytes + header->table_bytes;
/* Second is the CBMEM area (which usually includes the coreboot
table). */
cbmem_get_region(&baseptr, &size);
if (!baseptr || size == 0) {
printk(BIOS_WARNING, "FIT: CBMEM pointer/size not found!\n");
return;
}
reg_addrs[1] = (uintptr_t)baseptr;
reg_sizes[1] = size;
dt_add_reg_prop(coreboot_node, reg_addrs, reg_sizes, 2, addr_cells,
size_cells);
/* Expose board ID, SKU ID, and RAM code to payload.*/
if (board_id() != UNDEFINED_STRAPPING_ID)
dt_add_u32_prop(coreboot_node, "board-id", board_id());
if (sku_id() != UNDEFINED_STRAPPING_ID)
dt_add_u32_prop(coreboot_node, "sku-id", sku_id());
if (ram_code() != UNDEFINED_STRAPPING_ID)
dt_add_u32_prop(coreboot_node, "ram-code", ram_code());
}
/*
* Parse the uImage FIT, choose a configuration and extract images.
*/
@ -131,6 +193,9 @@ void fit_payload(struct prog *payload)
dt_apply_fixups(dt);
/* Insert coreboot specific information */
add_cb_fdt_data(dt);
/* Update device_tree */
#if defined(CONFIG_LINUX_COMMAND_LINE)
fit_update_chosen(dt, (char *)CONFIG_LINUX_COMMAND_LINE);

View File

@ -299,10 +299,15 @@ void cbmem_add_bootmem(void)
void *baseptr = NULL;
size_t size = 0;
imd_region_used(cbmem_get_imd(), &baseptr, &size);
cbmem_get_region(&baseptr, &size);
bootmem_add_range((uintptr_t)baseptr, size, BM_MEM_TABLE);
}
void cbmem_get_region(void **baseptr, size_t *size)
{
imd_region_used(cbmem_get_imd(), baseptr, size);
}
#if ENV_RAMSTAGE || (IS_ENABLED(CONFIG_EARLY_CBMEM_LIST) \
&& (ENV_POSTCAR || ENV_ROMSTAGE))
/*