Add 82Q35/P35/Q33/G33/G31/P31 support to inteltool.
The registers are (as far as I can tell) unchanged with respect to those of the PM965. Signed-off-by: Loïc Grenié <loic.grenie@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4905 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -39,6 +39,9 @@ static const struct {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" },
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@ -52,6 +52,9 @@
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#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
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#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
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#define PCI_DEVICE_ID_INTEL_PM965 0x2a00
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#define PCI_DEVICE_ID_INTEL_PM965 0x2a00
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#define PCI_DEVICE_ID_INTEL_82975X 0x277c
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#define PCI_DEVICE_ID_INTEL_82975X 0x277c
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#define PCI_DEVICE_ID_INTEL_82Q35 0x29b0
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#define PCI_DEVICE_ID_INTEL_82G33 0x29c0
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#define PCI_DEVICE_ID_INTEL_82Q33 0x29d0
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#define PCI_DEVICE_ID_INTEL_X58 0x3405
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#define PCI_DEVICE_ID_INTEL_X58 0x3405
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#define PCI_DEVICE_ID_INTEL_82443LX 0x7180
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#define PCI_DEVICE_ID_INTEL_82443LX 0x7180
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@ -40,6 +40,9 @@ int print_mchbar(struct pci_dev *nb)
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mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe;
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mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe;
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break;
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break;
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case PCI_DEVICE_ID_INTEL_PM965:
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case PCI_DEVICE_ID_INTEL_PM965:
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case PCI_DEVICE_ID_INTEL_82Q35:
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case PCI_DEVICE_ID_INTEL_82G33:
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case PCI_DEVICE_ID_INTEL_82Q33:
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mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
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mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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break;
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break;
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@ -39,6 +39,9 @@ int print_epbar(struct pci_dev *nb)
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epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
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epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
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break;
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break;
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case PCI_DEVICE_ID_INTEL_PM965:
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case PCI_DEVICE_ID_INTEL_PM965:
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case PCI_DEVICE_ID_INTEL_82Q35:
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case PCI_DEVICE_ID_INTEL_82G33:
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case PCI_DEVICE_ID_INTEL_82Q33:
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epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
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epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
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epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
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epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
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break;
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break;
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@ -86,6 +89,9 @@ int print_dmibar(struct pci_dev *nb)
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dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
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dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
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break;
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break;
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case PCI_DEVICE_ID_INTEL_PM965:
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case PCI_DEVICE_ID_INTEL_PM965:
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case PCI_DEVICE_ID_INTEL_82Q35:
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case PCI_DEVICE_ID_INTEL_82G33:
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case PCI_DEVICE_ID_INTEL_82Q33:
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dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
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dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
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dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
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dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
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break;
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break;
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@ -135,6 +141,9 @@ int print_pciexbar(struct pci_dev *nb)
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pciexbar_reg = pci_read_long(nb, 0x48);
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pciexbar_reg = pci_read_long(nb, 0x48);
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break;
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break;
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case PCI_DEVICE_ID_INTEL_PM965:
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case PCI_DEVICE_ID_INTEL_PM965:
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case PCI_DEVICE_ID_INTEL_82Q35:
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case PCI_DEVICE_ID_INTEL_82G33:
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case PCI_DEVICE_ID_INTEL_82Q33:
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pciexbar_reg = pci_read_long(nb, 0x60);
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pciexbar_reg = pci_read_long(nb, 0x60);
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pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
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pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
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break;
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break;
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