tegra132: Add special I2C6 init

I2C6 has a special mux in the SOR/DC domain, so there's a ton
of devices that need to be clocked, SOR unpowergated, and then
the I2C6 muxing done in the DPAUX_HYBRID_PADCTL register.

BUG=none
BRANCH=none
TEST=none, built rush/ryu AOK

Change-Id: Ibeeda763b7fb30fabaee85d03fbf7d5efb42a30a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0b4da98e20a89b045f2d5b5033a27cd7ab855f35
Original-Change-Id: I4aaa74ef1b3009da621d1a2ef6f79de8ebf545e2
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/212887
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8992
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/soc/nvidia/tegra132/Makefile.inc

@@ -30,6 +30,7 @@ romstage-y += clock.c
 romstage-y += reset.c
 romstage-y += spi.c
 romstage-y += i2c.c
+romstage-y += i2c6.c
 romstage-y += dma.c
 romstage-y += monotonic_timer.c
 romstage-y += padconfig.c

src/soc/nvidia/tegra132/i2c6.c

@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2014, NVIDIA CORPORATION.
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <soc/addressmap.h>
+#include <soc/clock.h>
+#include <soc/padconfig.h>
+#include <soc/nvidia/tegra/i2c.h>
+#include <soc/nvidia/tegra132/power.h>
+#include <soc/nvidia/tegra132/clk_rst.h>
+#include "delay.h"
+
+#define I2C6_BUS		5
+#define I2C6_PADCTL		0xC001
+#define DPAUX_HYBRID_PADCTL	0x545C0124
+
+static struct tegra_pmc_regs * const pmc = (void *)TEGRA_PMC_BASE;
+static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
+
+static int partition_clamp_on(int id)
+{
+	return read32(&pmc->clamp_status) & (1 << id);
+}
+
+static void remove_clamps(int id)
+{
+	if (!partition_clamp_on(id))
+		return;
+
+	/* Remove clamp */
+	write32((1 << id), &pmc->remove_clamping_cmd);
+
+	/* Wait for clamp off */
+	while (partition_clamp_on(id))
+		;
+}
+
+static void enable_sor_periphs(void)
+{
+	u32 lclks = CLK_L_HOST1X;
+	u32 hclks = CLK_H_MIPI_CAL | CLK_H_HDMI | CLK_H_DSI;
+	u32 uclks = CLK_U_DSIB;
+	u32 wclks = CLK_W_DP2 | CLK_W_HDA2HDMICODEC;
+	u32 xclks = CLK_X_DPAUX | CLK_X_SOR0 | CLK_X_HDMI_AUDIO;
+
+	clock_enable(lclks, hclks, uclks, 0, wclks, xclks);
+
+	/* Give clocks time to stabilize. */
+	udelay(IO_STABILIZATION_DELAY);
+}
+
+static void unreset_sor_periphs(void)
+{
+	u32 lclks = CLK_L_HOST1X;
+	u32 hclks = CLK_H_MIPI_CAL | CLK_H_HDMI | CLK_H_DSI;
+	u32 uclks = CLK_U_DSIB;
+	u32 wclks = CLK_W_DP2 | CLK_W_HDA2HDMICODEC;
+	u32 xclks = CLK_X_DPAUX | CLK_X_SOR0 | CLK_X_HDMI_AUDIO;
+
+	clock_clear_reset(lclks, hclks, uclks, 0, wclks, xclks);
+}
+
+void soc_configure_i2c6pad(void)
+{
+	/*
+	 * I2C6 on Tegra124/132 requires some special init.
+	 * The SOR block must be unpowergated, and several
+	 * display-based peripherals must be clocked and taken
+	 * out of reset so that a DPAUX register can be
+	 * configured to enable the I2C6 mux routing.
+	 */
+	power_ungate_partition(POWER_PARTID_SOR);
+	enable_sor_periphs();
+	remove_clamps(POWER_PARTID_SOR);
+	unreset_sor_periphs();
+
+	/* Host1X needs a valid clock source so DPAUX can be accessed */
+	clock_configure_source(host1x, PLLP, 204000);
+
+	/* Now we can write the I2C6 mux in DPAUX */
+	write32(I2C6_PADCTL, (void *)DPAUX_HYBRID_PADCTL);
+}

src/soc/nvidia/tegra132/include/soc/clock.h

@@ -146,6 +146,7 @@ enum {
 	CLK_W_CEC = 0x1 << 8,
 	CLK_W_XUSB_PADCTL = 0x1 << 14,
 	CLK_W_ENTROPY = 0x1 << 21,
+	CLK_W_DP2 = 0x1 << 24,
 	CLK_W_AMX0 = 0x1 << 25,
 	CLK_W_ADX0 = 0x1 << 26,
 	CLK_W_DVFS = 0x1 << 27,

src/soc/nvidia/tegra132/include/soc/padconfig.h

@@ -85,5 +85,7 @@ struct pad_config {
  * Configure the pads associated with entry according to the configuration.
  */
 void soc_configure_pads(const struct pad_config * const entries, size_t num);
+/* I2C6 requires special init as its pad lives int the SOR/DPAUX block */
+void soc_configure_i2c6pad(void);
 
 #endif /* __SOC_NVIDIA_TEGRA132_PAD_CFG_H */

src/soc/nvidia/tegra132/pmc.h

@@ -34,6 +34,7 @@ enum {
 	POWER_PARTID_CE0 = 14,
 	POWER_PARTID_C0NC = 15,
 	POWER_PARTID_C1NC = 16,
+	POWER_PARTID_SOR = 17,
 	POWER_PARTID_DIS = 18,
 	POWER_PARTID_DISB = 19,
 	POWER_PARTID_XUSBA = 20,