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southbridge/via: Spelling fixes 

Change-Id: I7efc441d3da10e48c8c79e4cd51885bb14eebd55
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7730
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Martin Roth 2014-12-09 13:49:05 -07:00 committed by Martin Roth
parent b348bb5cfb
commit 84422b1a20
15 changed files with 26 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/southbridge/via/common/via_early_smbus.h
View File

@ -24,7 +24,7 @@
*
* Functions defined in device/early/smbus.h are each implemented in a separate
* early_smbus_[func_name].c file. This makes it possible to override any of
* these functions by not including them in yout build, via Makefile.c. This is
* these functions by not including them in your build, via Makefile.c. This is
* useful when there is a need to work around chipset bugs.
*
* These implementations work with most via chipsets. Any VIA port should try

4
src/southbridge/via/k8t890/ctrl.c
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@ -122,7 +122,7 @@ static void vt8237r_vlink_init(struct device *dev)
/*
* This init code is valid only for the VT8237R! For different
* sounthbridges (e.g. VT8237A, VT8237S, VT8237 (without plus R)
* southbridges (e.g. VT8237A, VT8237S, VT8237 (without plus R)
* and VT8251) a different init code is required.
*/
@ -153,7 +153,7 @@ static void ctrl_init(struct device *dev)
{
print_debug("K8x8xx: Initializing V-Link to VT8237R sb: ");
/* TODO: Fix some ordering issue fo V-link set Rx77[6] and PCI1_Rx4F[0]
/* TODO: Fix some ordering issue for V-link set Rx77[6] and PCI1_Rx4F[0]
should to 1 */
/* C2P Read ACK Return Priority */

2
src/southbridge/via/vt8231/early_smbus.c
View File

@ -129,7 +129,7 @@ static void smbus_print_error(unsigned char host_status_register)
print_err_hex8(host_status_register);
print_err("\n");
if (host_status_register & (1 << 4)) {
print_err("Interrup/SMI# was Failed Bus Transaction\n");
print_err("Interrupt/SMI# was Failed Bus Transaction\n");
}
if (host_status_register & (1 << 3)) {
print_err("Bus Error\n");

6
src/southbridge/via/vt8231/ide.c
View File

@ -11,7 +11,7 @@ static void ide_init(struct device *dev)
unsigned char enables;
if (!conf->enable_native_ide) {
// Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
// Run the IDE controller in 'compatibility mode - i.e. don't use PCI
// interrupts. Using PCI ints confuses linux for some reason.
/* Setting reg 0x42 here does not work. It is set in mainboard/romstage.c
* It probably can only be changed while the IDE is disabled
@ -22,7 +22,7 @@ static void ide_init(struct device *dev)
printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n", __func__);
enables = pci_read_config8(dev, 0x42);
printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables);
enables &= ~0xc0; // compatability mode
enables &= ~0xc0; // compatibility mode
pci_write_config8(dev, 0x42, enables);
enables = pci_read_config8(dev, 0x42);
printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n", enables);
@ -85,7 +85,7 @@ static void ide_init(struct device *dev)
printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables);
if (!conf->enable_native_ide) {
// Use compatability mode - per award bios
// Use compatibility mode - per award bios
pci_write_config32(dev, 0x10, 0x0);
pci_write_config32(dev, 0x14, 0x0);
pci_write_config32(dev, 0x18, 0x0);

2
src/southbridge/via/vt8231/lpc.c
View File

@ -23,7 +23,7 @@ static void pci_routing_fixup(struct device *dev)
printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev);
if (dev) {
/* initialize PCI interupts - these assignments depend
/* initialize PCI interrupts - these assignments depend
on the PCB routing of PINTA-D
PINTA = IRQ11

2
src/southbridge/via/vt8235/early_serial.c
View File

@ -1,5 +1,5 @@
/*
* Enable the serial evices on the VIA
* Enable the serial devices on the VIA
*/

2
src/southbridge/via/vt8235/early_smbus.c
View File

@ -136,7 +136,7 @@ static void smbus_print_error(unsigned char host_status_register)
print_err_hex8(host_status_register);
print_err("\n");
if (host_status_register & (1 << 4)) {
print_err("Interrup/SMI# was Failed Bus Transaction\n");
print_err("Interrupt/SMI# was Failed Bus Transaction\n");
}
if (host_status_register & (1 << 3)) {
print_err("Bus Error\n");

6
src/southbridge/via/vt8235/ide.c
View File

@ -14,7 +14,7 @@ static void ide_init(struct device *dev)
/*if (!conf->enable_native_ide) { */
/*
* Run the IDE controller in 'compatiblity mode - i.e. don't
* Run the IDE controller in 'compatibility mode - i.e. don't
* use PCI interrupts. Using PCI ints confuses linux for some
* reason.
*/
@ -22,7 +22,7 @@ static void ide_init(struct device *dev)
__func__);
enables = pci_read_config8(dev, 0x42);
printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables);
enables &= ~0xc0; // compatability mode
enables &= ~0xc0; // compatibility mode
pci_write_config8(dev, 0x42, enables);
enables = pci_read_config8(dev, 0x42);
printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n",
@ -85,7 +85,7 @@ static void ide_init(struct device *dev)
printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables);
if (!conf->enable_native_ide) {
// Use compatability mode - per award bios
// Use compatibility mode - per award bios
pci_write_config32(dev, 0x10, 0x0);
pci_write_config32(dev, 0x14, 0x0);
pci_write_config32(dev, 0x18, 0x0);

8
src/southbridge/via/vt8235/lpc.c
View File

@ -8,7 +8,7 @@
#include <arch/ioapic.h>
#include "chip.h"
/* The epia-m is really short on interrupts available, so PCI interupts A & D are ganged togther and so are B & C.
/* The epia-m is really short on interrupts available, so PCI interrupts A & D are ganged together and so are B & C.
This is how the Award bios sets it up too.
epia can be more generous as it does not need to reserve interrupts for cardbus devices, but if changed then
make sure that ACPI dsdt is changed to suit.
@ -19,7 +19,7 @@
IRQ 3 = COM 2
IRQ 4 = COM 1
IRQ 5 = available for PCI interrupts
IRQ 6 = floppy or availbale for PCI if floppy controller disabled
IRQ 6 = floppy or available for PCI if floppy controller disabled
IRQ 7 = LPT or available if LPT port disabled
IRQ 8 = rtc
IRQ 9 = available for PCI interrupts
@ -115,7 +115,7 @@ static void setup_pm(device_t dev)
// set ACPI irq to 5
pci_write_config8(dev, 0x82, 0x45);
// primary interupt channel
// primary interrupt channel
pci_write_config16(dev, 0x84, 0x30f2);
// throttle / stop clock control
@ -212,7 +212,7 @@ static void vt8235_init(struct device *dev)
cmos_init(0);
}
/* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this
/* total kludge to get lxb to call our children's set/enable functions - these are not called unless this
device has a resource to set - so set a dummy one */
static void vt8235_read_resources(device_t dev)
{

2
src/southbridge/via/vt8235/vt8235.c
View File

@ -64,7 +64,7 @@ static void vt8235_enable(struct device *dev)
printk(BIOS_DEBUG, "Initialising Devices\n");
/* make sure interupt controller is configured before keyboard init */
/* make sure interrupt controller is configured before keyboard init */
setup_i8259();
/* enable RTC and ethernet */

2
src/southbridge/via/vt8237r/chip.h
View File

@ -40,7 +40,7 @@ struct southbridge_via_vt8237r_config {
* 7 USB Device Mode 1=dis
* 6 Reserved
* 5 Internal LAN Controller Clock Gating 1=gated
* 4 Internal LAN Controller 1=di
* 4 Internal LAN Controller 1=dis
* 3 Internal RTC 1=en
* 2 Internal PS2 Mouse 1=en
* 1 Internal KBC Configuration 0=dis ports 0x2e/0x2f off 0xe0-0xef

4
src/southbridge/via/vt8237r/ctrl.c
View File

@ -136,7 +136,7 @@ static void vt8237s_vlink_init(struct device *dev)
/*
* This init code is valid only for the VT8237S! For different
* sounthbridges (e.g. VT8237A, VT8237S, VT8237R (without plus R)
* southbridges (e.g. VT8237A, VT8237S, VT8237R (without plus R)
* and VT8251) a different init code is required.
*/
@ -211,7 +211,7 @@ static void vt8237a_vlink_init(struct device *dev)
/*
* This init code is valid only for the VT8237A! For different
* sounthbridges (e.g. VT8237S, VT8237R and VT8251) a different
* southbridges (e.g. VT8237S, VT8237R and VT8251) a different
* init code is required.
*
* FIXME: This is based on vt8237r_vlink_init() in

2
src/southbridge/via/vt8237r/early_smbus.c
View File

@ -282,7 +282,7 @@ void vt8237_sb_enable_fid_vid(void)
/* chipset-specific parts */
/* VLINK: FIXME: can we drop the devid check and just look for the VLINK device? */
/* VLINK: FIXME: can we drop the device check and just look for the VLINK device? */
if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC ||
devid == PCI_DEVICE_ID_VIA_VT8237A_LPC) {
devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,

6
src/southbridge/via/vt8237r/lpc.c
View File

@ -165,10 +165,10 @@ static void setup_pm(device_t dev)
pci_write_config8(dev, 0x82, 0x40 | VT8237R_ACPI_IRQ);
#if CONFIG_EPIA_VT8237R_INIT
/* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
/* Primary interrupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
pci_write_config16(dev, 0x84, 0x3052);
#else
/* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
/* Primary interrupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
pci_write_config16(dev, 0x84, 0x30b2);
#endif
@ -358,7 +358,7 @@ static void vt8237a_init(struct device *dev)
{
/*
* FIXME: This is based on vt8237s_init() and the values the AMI
* BIOS on my M2V wrote to these registers (by loking
* BIOS on my M2V wrote to these registers (by looking
* at lspci -nxxx output).
* Works for me.
*/

2
src/southbridge/via/vt8237r/smihandler.c
View File

@ -242,7 +242,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
if (southbridge_smi[i])
southbridge_smi[i](node, state_save);
else {
printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no "
"handler available.\n", i);
dump = 1;
}