soc/amd/common/block/lpc/espi_util: make eSPI pin setup failure nonfatal
Improve the eSPI pin configuration setup so that a failure in there won't call die() and stop booting at this point, but return an error to the caller so that the rest of the eSPI configuration will be skipped. This will prevent an early boot failure if the EC is missing or the eSPI interface is in a non-functional state. Also slightly shorten the function names so that the code still fits into 96 chars. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ice2d3a791d6a464eff4fb69d02aeca0bfe580be2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70730 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
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@ -680,7 +680,7 @@ static enum cb_err espi_get_general_configuration(uint32_t *config)
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return CB_SUCCESS;
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}
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static void espi_set_io_mode_config(enum espi_io_mode mb_io_mode, uint32_t slave_caps,
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static enum cb_err espi_set_io_mode_cfg(enum espi_io_mode mb_io_mode, uint32_t slave_caps,
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uint32_t *slave_config, uint32_t *ctrlr_config)
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{
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switch (mb_io_mode) {
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@ -706,11 +706,13 @@ static void espi_set_io_mode_config(enum espi_io_mode mb_io_mode, uint32_t slave
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*ctrlr_config |= ESPI_IO_MODE_SINGLE;
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break;
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default:
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die("No supported eSPI I/O modes!\n");
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printk(BIOS_ERR, "No supported eSPI I/O modes!\n");
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return CB_ERR;
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}
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return CB_SUCCESS;
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}
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static void espi_set_op_freq_config(enum espi_op_freq mb_op_freq, uint32_t slave_caps,
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static enum cb_err espi_set_op_freq_cfg(enum espi_op_freq mb_op_freq, uint32_t slave_caps,
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uint32_t *slave_config, uint32_t *ctrlr_config)
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{
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int slave_max_speed_mhz = espi_slave_max_speed_mhz_supported(slave_caps);
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@ -744,30 +746,35 @@ static void espi_set_op_freq_config(enum espi_op_freq mb_op_freq, uint32_t slave
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}
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__fallthrough;
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default:
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die("No supported eSPI Operating Frequency!\n");
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printk(BIOS_ERR, "No supported eSPI Operating Frequency!\n");
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return CB_ERR;
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}
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return CB_SUCCESS;
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}
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static void espi_set_alert_pin_config(enum espi_alert_pin alert_pin, uint32_t slave_caps,
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static enum cb_err espi_set_alert_pin_cfg(enum espi_alert_pin alert_pin, uint32_t slave_caps,
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uint32_t *slave_config, uint32_t *ctrlr_config)
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{
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switch (alert_pin) {
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case ESPI_ALERT_PIN_IN_BAND:
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*slave_config |= ESPI_SLAVE_ALERT_MODE_IO1;
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return;
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return CB_SUCCESS;
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case ESPI_ALERT_PIN_PUSH_PULL:
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*slave_config |= ESPI_SLAVE_ALERT_MODE_PIN | ESPI_SLAVE_PUSH_PULL_ALERT_SEL;
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*ctrlr_config |= ESPI_ALERT_MODE;
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return;
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return CB_SUCCESS;
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case ESPI_ALERT_PIN_OPEN_DRAIN:
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if (!(slave_caps & ESPI_SLAVE_OPEN_DRAIN_ALERT_SUPP))
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die("eSPI peripheral does not support open drain alert!");
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if (!(slave_caps & ESPI_SLAVE_OPEN_DRAIN_ALERT_SUPP)) {
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printk(BIOS_ERR, "eSPI peripheral does not support open drain alert!");
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return CB_ERR;
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}
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*slave_config |= ESPI_SLAVE_ALERT_MODE_PIN | ESPI_SLAVE_OPEN_DRAIN_ALERT_SEL;
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*ctrlr_config |= ESPI_ALERT_MODE;
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return;
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return CB_SUCCESS;
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default:
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die("Unknown espi alert config: %u!\n", alert_pin);
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printk(BIOS_ERR, "Unknown espi alert config: %u!\n", alert_pin);
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return CB_ERR;
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}
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}
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@ -782,9 +789,15 @@ static enum cb_err espi_set_general_configuration(const struct espi_config *mb_c
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ctrlr_config |= ESPI_CRC_CHECKING_EN;
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}
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espi_set_alert_pin_config(mb_cfg->alert_pin, slave_caps, &slave_config, &ctrlr_config);
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espi_set_io_mode_config(mb_cfg->io_mode, slave_caps, &slave_config, &ctrlr_config);
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espi_set_op_freq_config(mb_cfg->op_freq_mhz, slave_caps, &slave_config, &ctrlr_config);
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if (espi_set_alert_pin_cfg(mb_cfg->alert_pin, slave_caps, &slave_config, &ctrlr_config)
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!= CB_SUCCESS)
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return CB_ERR;
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if (espi_set_io_mode_cfg(mb_cfg->io_mode, slave_caps, &slave_config, &ctrlr_config)
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!= CB_SUCCESS)
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return CB_ERR;
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if (espi_set_op_freq_cfg(mb_cfg->op_freq_mhz, slave_caps, &slave_config, &ctrlr_config)
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!= CB_SUCCESS)
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return CB_ERR;
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if (CONFIG(ESPI_DEBUG))
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printk(BIOS_INFO, "Setting general configuration: slave: 0x%x controller: 0x%x\n",
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