soc/intel/cannonlake: Add postcar stage support
Initialize postcar frame once finish FSP memoryinit This patch was merged too early and reverted. Originally reviewed on https://review.coreboot.org/#/c/20534 Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20688 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -43,6 +43,7 @@ postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
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postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c
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postcar-$(CONFIG_FSP_CAR) += util.c
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postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c
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postcar-y += hand_off_block.c
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CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include
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@ -18,6 +18,8 @@ config CPU_SPECIFIC_OPTIONS
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select HAVE_MONOTONIC_TIMER
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select INTEL_CAR_NEM_ENHANCED
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select PLATFORM_USES_FSP2_0
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select POSTCAR_CONSOLE
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select POSTCAR_STAGE
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select REG_SCRIPT
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select RELOCATABLE_RAMSTAGE
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select SOC_INTEL_COMMON
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@ -76,4 +78,13 @@ config CPU_BCLK_MHZ
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int
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default 100
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# Clock divider parameters for 115200 baud rate
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config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
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hex
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default 0x30
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config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
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hex
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default 0xc35
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endif
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@ -12,15 +12,19 @@ bootblock-y += bootblock/pch.c
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bootblock-y += bootblock/report_platform.c
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bootblock-y += gpio.c
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bootblock-y += memmap.c
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bootblock-$(CONFIG_UART_DEBUG) += uart.c
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romstage-y += memmap.c
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romstage-y += reset.c
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romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
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romstage-$(CONFIG_UART_DEBUG) += uart.c
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ramstage-y += cbmem.c
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ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
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ramstage-y += systemagent.c
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ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
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ramstage-$(CONFIG_UART_DEBUG) += uart.c
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postcar-y += memmap.c
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postcar-$(CONFIG_UART_DEBUG) += uart.c
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CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20
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CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake
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@ -14,6 +14,7 @@
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*/
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#include <arch/io.h>
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#include <cpu/x86/mtrr.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <fsp/util.h>
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@ -25,6 +26,8 @@
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asmlinkage void car_stage_entry(void)
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{
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bool s3wake;
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struct postcar_frame pcf;
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uintptr_t top_of_ram;
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struct chipset_power_state *ps;
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console_init();
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@ -36,7 +39,25 @@ asmlinkage void car_stage_entry(void)
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timestamp_add_now(TS_START_ROMSTAGE);
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s3wake = ps->prev_sleep_state == ACPI_S3;
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fsp_memory_init(s3wake);
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die("Get out from FSP memoryinit. \n");
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if (postcar_frame_init(&pcf, 1 * KiB))
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die("Unable to initialize postcar frame.\n");
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/*
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* We need to make sure ramstage will be run cached. At this
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* point exact location of ramstage in cbmem is not known.
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* Instruct postcar to cache 16 megs under cbmem top which is
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* a safe bet to cover ramstage.
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*/
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top_of_ram = (uintptr_t) cbmem_top();
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printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
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top_of_ram -= 16*MiB;
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postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
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/* Cache the ROM as WP just below 4GiB. */
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postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1,
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CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
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run_postcar_phase(&pcf);
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}
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void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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@ -13,6 +13,8 @@
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* GNU General Public License for more details.
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*/
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#define __SIMPLE_DEVICE__
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#include <assert.h>
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#include <console/uart.h>
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#include <device/pci_def.h>
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@ -25,10 +27,6 @@
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#include <soc/pcr_ids.h>
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#include <soc/iomap.h>
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/* Clock divider parameters for 115200 baud rate */
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#define CLK_M_VAL 0x30
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#define CLK_N_VAL 0xc35
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static const struct port {
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struct pad_config pads[2]; /* just TX and RX */
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device_t dev;
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@ -56,12 +54,14 @@ void pch_uart_init(void)
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p = &uart_ports[CONFIG_UART_FOR_CONSOLE];
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base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
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uart_common_init(p->dev, base, CLK_M_VAL, CLK_N_VAL);
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uart_common_init(p->dev, base);
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gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads));
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}
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#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)
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uintptr_t uart_platform_base(int idx)
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{
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/* We can only have one serial console at a time */
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return UART_DEBUG_BASE_ADDRESS;
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}
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#endif
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