soc/intel/cannonlake: Add postcar stage support

Initialize postcar frame once finish FSP memoryinit

This patch was merged too early and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20534

Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20688
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lijian Zhao 2017-07-11 12:33:22 -07:00 committed by Aaron Durbin
parent e2ef3cf8e3
commit 8465a81e81
5 changed files with 45 additions and 8 deletions

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@ -43,6 +43,7 @@ postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c
postcar-$(CONFIG_FSP_CAR) += util.c
postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c
postcar-y += hand_off_block.c
CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include

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@ -18,6 +18,8 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_MONOTONIC_TIMER
select INTEL_CAR_NEM_ENHANCED
select PLATFORM_USES_FSP2_0
select POSTCAR_CONSOLE
select POSTCAR_STAGE
select REG_SCRIPT
select RELOCATABLE_RAMSTAGE
select SOC_INTEL_COMMON
@ -76,4 +78,13 @@ config CPU_BCLK_MHZ
int
default 100
# Clock divider parameters for 115200 baud rate
config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
hex
default 0x30
config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
hex
default 0xc35
endif

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@ -12,15 +12,19 @@ bootblock-y += bootblock/pch.c
bootblock-y += bootblock/report_platform.c
bootblock-y += gpio.c
bootblock-y += memmap.c
bootblock-$(CONFIG_UART_DEBUG) += uart.c
romstage-y += memmap.c
romstage-y += reset.c
romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
romstage-$(CONFIG_UART_DEBUG) += uart.c
ramstage-y += cbmem.c
ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
ramstage-y += systemagent.c
ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
ramstage-$(CONFIG_UART_DEBUG) += uart.c
postcar-y += memmap.c
postcar-$(CONFIG_UART_DEBUG) += uart.c
CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake

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@ -14,6 +14,7 @@
*/
#include <arch/io.h>
#include <cpu/x86/mtrr.h>
#include <cbmem.h>
#include <console/console.h>
#include <fsp/util.h>
@ -25,6 +26,8 @@
asmlinkage void car_stage_entry(void)
{
bool s3wake;
struct postcar_frame pcf;
uintptr_t top_of_ram;
struct chipset_power_state *ps;
console_init();
@ -36,7 +39,25 @@ asmlinkage void car_stage_entry(void)
timestamp_add_now(TS_START_ROMSTAGE);
s3wake = ps->prev_sleep_state == ACPI_S3;
fsp_memory_init(s3wake);
die("Get out from FSP memoryinit. \n");
if (postcar_frame_init(&pcf, 1 * KiB))
die("Unable to initialize postcar frame.\n");
/*
* We need to make sure ramstage will be run cached. At this
* point exact location of ramstage in cbmem is not known.
* Instruct postcar to cache 16 megs under cbmem top which is
* a safe bet to cover ramstage.
*/
top_of_ram = (uintptr_t) cbmem_top();
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
top_of_ram -= 16*MiB;
postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1,
CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
run_postcar_phase(&pcf);
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)

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@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
#define __SIMPLE_DEVICE__
#include <assert.h>
#include <console/uart.h>
#include <device/pci_def.h>
@ -25,10 +27,6 @@
#include <soc/pcr_ids.h>
#include <soc/iomap.h>
/* Clock divider parameters for 115200 baud rate */
#define CLK_M_VAL 0x30
#define CLK_N_VAL 0xc35
static const struct port {
struct pad_config pads[2]; /* just TX and RX */
device_t dev;
@ -56,12 +54,14 @@ void pch_uart_init(void)
p = &uart_ports[CONFIG_UART_FOR_CONSOLE];
base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
uart_common_init(p->dev, base, CLK_M_VAL, CLK_N_VAL);
uart_common_init(p->dev, base);
gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads));
}
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)
uintptr_t uart_platform_base(int idx)
{
/* We can only have one serial console at a time */
return UART_DEBUG_BASE_ADDRESS;
}
#endif