soc/qualcomm: Fill coreboot table with PCIe info

In order to pass PCIe base address to payloads, implement pcie_fill_lb()
to fill coreboot table with PCIe info.

BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe endpoint
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
 CLI prompt.

Output logs:
 ->dpch: storage init
   Initializing NVMe controller 1e0f:0001
   Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
   Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
   *  0: NVMe Namespace 1
    1 devices total

Also verified NVMe boot path that is depthcharge is able to load the
kernel image from NVMe storage.

Change-Id: I1ca2be55b98c8d1b86576072078cdda02ac55940
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57614
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/soc/qualcomm/common/pcie_common.c

@@ -410,6 +410,17 @@ static enum cb_err qcom_dw_pcie_enable(struct qcom_pcie_cntlr_t *pcie)
 	return CB_SUCCESS;
 }
 
+/**
+ * Fill coreboot table with PCIe info.
+ * It allows exporting this info to payloads.
+ */
+enum cb_err lb_fill_pcie(struct lb_pcie *pcie)
+{
+	pcie_cntlr_cfg_t *pcierc = qcom_pcie_cfg.cntlr_cfg;
+	pcie->ctrl_base = (uintptr_t)pcierc->dbi_base;
+	return CB_SUCCESS;
+}
+
 /* map_bus function for mapping pcie_s_{read/write}_configXX() functions */
 volatile union pci_bank *pci_map_bus(pci_devfn_t dev)
 {