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nb/intel/haswell: Create RMRR for iGPU 

Taken from Broadwell.

Change-Id: I246fdc1473bf8949073377d03622026bd3e6aafa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Angel Pons 2020-10-29 21:39:52 +01:00 committed by Patrick Georgi
parent be6ad1ace0
commit 849104f2fb
1 changed files with 21 additions and 1 deletions
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22
src/northbridge/intel/haswell/acpi.c
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@ -26,8 +26,13 @@ static unsigned long acpi_fill_dmar(unsigned long current)
const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1;
/* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten && !MCHBAR32(GFXVTBAR + 4)) {
const bool emit_igd =
igfx_dev && igfx_dev->enabled &&
gfxvtbar && gfxvten &&
!MCHBAR32(GFXVTBAR + 4);
/* First, add DRHD entries */
if (emit_igd) {
const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
@ -51,6 +56,21 @@ static unsigned long acpi_fill_dmar(unsigned long current)
acpi_dmar_drhd_fixup(tmp, current);
}
/* Then, add RMRR entries after all DRHD entries */
if (emit_igd) {
const unsigned long tmp = current;
const struct device *sa_dev = pcidev_on_root(0, 0);
/* Bit 0 is lock bit, not part of address */
const u32 tolud = pci_read_config32(sa_dev, TOLUD) & ~1;
const u32 bgsm = pci_read_config32(sa_dev, BGSM) & ~1;
current += acpi_create_dmar_rmrr(current, 0, bgsm, tolud - 1);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_rmrr_fixup(tmp, current);
}
return current;
}