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nyan*: merge a couple of sor setting difference from kernel driver 

BRANCH=none
BUG=chrome-os-partner:27413
TEST=build nyan and nyan_big. nyan display works fine.
         nyan_big display still does't work until all related
         patches are built in. (CL:194739)

Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>

Original-Change-Id: Ic5d977f695be127693f1ecc3ba52d478f524d20f
Original-Reviewed-on: https://chromium-review.googlesource.com/194737
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Original-Tested-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit ef3208d8ff3c3dcfaeda9c0146bf1ae920682dea)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ide1cd28ecc0ae1cd4d8603a52975592daee4bce8
Reviewed-on: http://review.coreboot.org/7766
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Jimmy Zhang 2014-04-14 12:15:38 -07:00 committed by Marc Jones
parent f682ad0ebb
commit 84b8be6a97
1 changed files with 18 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/soc/nvidia/tegra124/sor.c
View File

@ -248,6 +248,23 @@ void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor,
tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), reg_val); tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), reg_val);
} }
static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div,
u32 pwm_dutycycle)
{
tegra_sor_writel(sor, NV_SOR_PWM_DIV, pwm_div);
tegra_sor_writel(sor, NV_SOR_PWM_CTL,
(pwm_dutycycle & NV_SOR_PWM_CTL_DUTY_CYCLE_MASK) |
NV_SOR_PWM_CTL_SETTING_NEW_TRIGGER);
if (tegra_dc_sor_poll_register(sor, NV_SOR_PWM_CTL,
NV_SOR_PWM_CTL_SETTING_NEW_SHIFT,
NV_SOR_PWM_CTL_SETTING_NEW_DONE,
100, TEGRA_SOR_TIMEOUT_MS * 1000)) {
printk(BIOS_ERR,
"dp: timeout while waiting for SOR PWM setting\n");
}
}
static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor, static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor,
const struct tegra_dc_dp_link_config *link_cfg) const struct tegra_dc_dp_link_config *link_cfg)
{ {
@ -274,11 +291,6 @@ static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor,
tegra_sor_writel(sor, NV_SOR_DP_CONFIG(sor->portnum), reg_val); tegra_sor_writel(sor, NV_SOR_DP_CONFIG(sor->portnum), reg_val);
/* enable CRC */
reg_val = NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_EN <<
NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_SHIFT;
tegra_sor_writel(sor, NV_SOR_CRC_CNTRL, reg_val);
/* program h/vblank sym */ /* program h/vblank sym */
tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_HBLANK_SYMBOLS, tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_HBLANK_SYMBOLS,
NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK, link_cfg->hblank_sym); NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK, link_cfg->hblank_sym);
@ -558,6 +570,7 @@ static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
2 << NV_SOR_CSTM_ROTCLK_SHIFT | 2 << NV_SOR_CSTM_ROTCLK_SHIFT |
(is_lvds ? NV_SOR_CSTM_LVDS_EN_ENABLE : (is_lvds ? NV_SOR_CSTM_LVDS_EN_ENABLE :
NV_SOR_CSTM_LVDS_EN_DISABLE)); NV_SOR_CSTM_LVDS_EN_DISABLE));
tegra_dc_sor_config_pwm(sor, 1024, 1024);
} }
static void tegra_dc_sor_enable_dc(struct tegra_dc_sor_data *sor) static void tegra_dc_sor_enable_dc(struct tegra_dc_sor_data *sor)
@ -571,7 +584,6 @@ static void tegra_dc_sor_enable_dc(struct tegra_dc_sor_data *sor)
WRITEL(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt); WRITEL(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt);
/* Enable DC */ /* Enable DC */
WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd);
WRITEL(reg_val, &disp_ctrl->cmd.state_access); WRITEL(reg_val, &disp_ctrl->cmd.state_access);
} }