From 84bf089f6a769a88db9717787eab078b00aaafb7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Sun, 28 Oct 2018 02:48:25 +0200 Subject: [PATCH] Documentation/mainboard: Add emulation/spike-riscv.md MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the usage instructions from their ad-hoc place in Kconfig.name to the Documentation directory, and expand them a bit. Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/28874 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Philipp Hug --- .../mainboard/emulation/spike-riscv.md | 23 +++++++++++++++++++ Documentation/mainboard/index.md | 6 +++++ .../emulation/spike-riscv/Kconfig.name | 4 ---- 3 files changed, 29 insertions(+), 4 deletions(-) create mode 100644 Documentation/mainboard/emulation/spike-riscv.md diff --git a/Documentation/mainboard/emulation/spike-riscv.md b/Documentation/mainboard/emulation/spike-riscv.md new file mode 100644 index 0000000000..55e87d9cc9 --- /dev/null +++ b/Documentation/mainboard/emulation/spike-riscv.md @@ -0,0 +1,23 @@ +# Spike RISC-V emulator + +[Spike], also known as riscv-isa-sim, is a commonly used [RISC-V] emulator. + + +## Installation + +- Download `riscv-fesvr` and `riscv-isa-sim` from +- Apply the two patches in , + which are necessary in order to have a serial console +- Compile `riscv-fesvr` and then `riscv-isa-sim` + + +## Building coreboot and running it in Spike + +- Configure coreboot and run `make` as usual +- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to + convert coreboot to an ELF that Spike can load +- Run `spike -m1024 build/coreboot.elf` + + +[Spike]: https://github.com/riscv/riscv-isa-sim +[RISC-V]: https://riscv.org/ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index c346a3b8f0..c1e5262a98 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -10,6 +10,12 @@ This section contains documentation about coreboot on specific mainboards. - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md) +## Emulation + +The boards in this section are not real mainboards, but emulators. + +- [Spike RISC-V emulator](emulation/spike-riscv.md) + ## Foxconn - [D41S](foxconn/d41s.md) diff --git a/src/mainboard/emulation/spike-riscv/Kconfig.name b/src/mainboard/emulation/spike-riscv/Kconfig.name index 3a82ab1a66..17549c6ebb 100644 --- a/src/mainboard/emulation/spike-riscv/Kconfig.name +++ b/src/mainboard/emulation/spike-riscv/Kconfig.name @@ -1,7 +1,3 @@ config BOARD_EMULATION_SPIKE_RISCV bool "SPIKE riscv" help - To run coreboot in spike: - * run "make" as usual - * util/riscv/make-spike-elf.sh build/coreboot.{rom,elf} - * spike -m1024 build/coreboot.elf