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soc/intel/ehl: Fix incorrect access to MAC_MDIO_DATA register 

Function 'setbits16' performs an 'OR' operation with the new data and
the origin register entry. This can lead to an incorrect value in the
register which can then lead to issues.

Change-Id: I0212420be770e2ffdabebbfaf5dfbf8d99d25915
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This commit is contained in:
Mario Scheithauer 2022-10-07 11:27:56 +02:00 committed by Felix Singer
parent d8fd2deda1
commit 84dbace1ea
1 changed files with 1 additions and 1 deletions
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src/soc/intel/elkhartlake/tsn_gbe.c
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@ -72,7 +72,7 @@ void tsn_mdio_write(void *base, uint8_t phy_adr, uint8_t reg_adr, uint16_t data)
{ {
enum cb_err status; enum cb_err status;
setbits16(base + TSN_MAC_MDIO_DATA, data); write16(base + TSN_MAC_MDIO_DATA, data);
clrsetbits32(base + TSN_MAC_MDIO_ADR, TSN_MAC_MDIO_ADR_MASK, clrsetbits32(base + TSN_MAC_MDIO_ADR, TSN_MAC_MDIO_ADR_MASK,
TSN_MAC_PHYAD(phy_adr) | TSN_MAC_REGAD(reg_adr) TSN_MAC_PHYAD(phy_adr) | TSN_MAC_REGAD(reg_adr)
| TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_62 | TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_62