From 84e6123d7e25862655b1ea92ea3e14bc9586429c Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 12 Dec 2022 07:39:15 +0100 Subject: [PATCH] soc/intel/braswell/acpi: Replace Store(a,b) with ASL 2.0 syntax Replace `Store (a, b)` with `b = a`. Change-Id: I2dd154c3d4e152a14783ea82e08a7d1257abebc3 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/70687 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- src/soc/intel/braswell/acpi/dptf/charger.asl | 6 +-- src/soc/intel/braswell/acpi/dptf/cpu.asl | 6 +-- src/soc/intel/braswell/acpi/dptf/thermal.asl | 2 +- src/soc/intel/braswell/acpi/irqlinks.asl | 48 ++++++++++---------- src/soc/intel/braswell/acpi/lpc.asl | 2 +- src/soc/intel/braswell/acpi/lpe.asl | 6 +-- src/soc/intel/braswell/acpi/lpss.asl | 22 ++++----- src/soc/intel/braswell/acpi/scc.asl | 6 +-- src/soc/intel/braswell/acpi/southcluster.asl | 18 ++++---- 9 files changed, 58 insertions(+), 58 deletions(-) diff --git a/src/soc/intel/braswell/acpi/dptf/charger.asl b/src/soc/intel/braswell/acpi/dptf/charger.asl index fb258f1cd9..61672ba7ed 100644 --- a/src/soc/intel/braswell/acpi/dptf/charger.asl +++ b/src/soc/intel/braswell/acpi/dptf/charger.asl @@ -26,7 +26,7 @@ Device (TCHG) Method (PPPC) { /* Convert size of PPSS table to index */ - Store (SizeOf (\_SB.CHPS), Local0) + Local0 = SizeOf (\_SB.CHPS) Local0-- /* Check if charging is disabled (AC removed) */ @@ -45,8 +45,8 @@ Device (TCHG) Method (SPPC, 1) { /* Retrieve Control (index 4) for specified PPSS level */ - Store (DeRefOf (Index (DeRefOf (Index - (\_SB.CHPS, ToInteger (Arg0))), 4)), Local0) + Local0 = DeRefOf (Index (DeRefOf (Index + (\_SB.CHPS, ToInteger (Arg0))), 4)) /* Pass Control value to EC to limit charging */ \_SB.PCI0.LPCB.EC0.CHGS (Local0) diff --git a/src/soc/intel/braswell/acpi/dptf/cpu.asl b/src/soc/intel/braswell/acpi/dptf/cpu.asl index 7af5b6b6b3..7a8511fd00 100644 --- a/src/soc/intel/braswell/acpi/dptf/cpu.asl +++ b/src/soc/intel/braswell/acpi/dptf/cpu.asl @@ -100,7 +100,7 @@ Device (B0DB) Method (_TDL) { If (CondRefOf (\_SB.CP00._TSS)) { - Store (SizeOf (\_SB.CP00._TSS ()), Local0) + Local0 = SizeOf (\_SB.CP00._TSS ()) Local0-- Return (Local0) } Else { @@ -119,7 +119,7 @@ Device (B0DB) Method (SPPC, 1) { - Store (Arg0, \PPCM) + \PPCM = Arg0 /* Notify OS to re-read _PPC limit on each CPU */ \PPCN () @@ -143,7 +143,7 @@ Device (B0DB) If (CondRefOf (\_SB.MPDL)) { Return (\_SB.MPDL) } ElseIf (CondRefOf (\_SB.CP00._PSS)) { - Store (SizeOf (\_SB.CP00._PSS ()), Local0) + Local0 = SizeOf (\_SB.CP00._PSS ()) Local0-- Return (Local0) } Else { diff --git a/src/soc/intel/braswell/acpi/dptf/thermal.asl b/src/soc/intel/braswell/acpi/dptf/thermal.asl index d2991bcf7f..0f5d90ff23 100644 --- a/src/soc/intel/braswell/acpi/dptf/thermal.asl +++ b/src/soc/intel/braswell/acpi/dptf/thermal.asl @@ -6,7 +6,7 @@ #if CONFIG(EC_SUPPORTS_DPTF_TEVT) Method (TEVT, 1, NotSerialized) { - Store (ToInteger (Arg0), Local0) + Local0 = ToInteger (Arg0) #ifdef DPTF_TSR0_SENSOR_ID If (Local0 == DPTF_TSR0_SENSOR_ID) { diff --git a/src/soc/intel/braswell/acpi/irqlinks.asl b/src/soc/intel/braswell/acpi/irqlinks.asl index 508a7218fe..42fc97e6b2 100644 --- a/src/soc/intel/braswell/acpi/irqlinks.asl +++ b/src/soc/intel/braswell/acpi/irqlinks.asl @@ -8,7 +8,7 @@ Device (LNKA) /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTA) + PRTA = 0x80 } /* Possible Resource Settings for this Link */ @@ -28,7 +28,7 @@ Device (LNKA) CreateWordField(RTLA, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = Zero /* Set the bit from PRTA */ ShiftLeft(1, And(PRTA, 0x0f), IRQ0) @@ -45,7 +45,7 @@ Device (LNKA) FindSetRightBit(IRQ0, Local0) Local0-- - Store(Local0, PRTA) + PRTA = Local0 } /* Status */ @@ -67,7 +67,7 @@ Device (LNKB) /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTB) + PRTB = 0x80 } /* Possible Resource Settings for this Link */ @@ -87,7 +87,7 @@ Device (LNKB) CreateWordField(RTLB, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = Zero /* Set the bit from PRTB */ ShiftLeft(1, And(PRTB, 0x0f), IRQ0) @@ -104,7 +104,7 @@ Device (LNKB) FindSetRightBit(IRQ0, Local0) Local0-- - Store(Local0, PRTB) + PRTB = Local0 } /* Status */ @@ -126,7 +126,7 @@ Device (LNKC) /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTC) + PRTC = 0x80 } /* Possible Resource Settings for this Link */ @@ -146,7 +146,7 @@ Device (LNKC) CreateWordField(RTLC, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = Zero /* Set the bit from PRTC */ ShiftLeft(1, And(PRTC, 0x0f), IRQ0) @@ -163,7 +163,7 @@ Device (LNKC) FindSetRightBit(IRQ0, Local0) Local0-- - Store(Local0, PRTC) + PRTC = Local0 } /* Status */ @@ -185,7 +185,7 @@ Device (LNKD) /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTD) + PRTD = 0x80 } /* Possible Resource Settings for this Link */ @@ -205,7 +205,7 @@ Device (LNKD) CreateWordField(RTLD, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = Zero /* Set the bit from PRTD */ ShiftLeft(1, And(PRTD, 0x0f), IRQ0) @@ -222,7 +222,7 @@ Device (LNKD) FindSetRightBit(IRQ0, Local0) Local0-- - Store(Local0, PRTD) + PRTD = Local0 } /* Status */ @@ -244,7 +244,7 @@ Device (LNKE) /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTE) + PRTE = 0x80 } /* Possible Resource Settings for this Link */ @@ -264,7 +264,7 @@ Device (LNKE) CreateWordField(RTLE, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = Zero /* Set the bit from PRTE */ ShiftLeft(1, And(PRTE, 0x0f), IRQ0) @@ -281,7 +281,7 @@ Device (LNKE) FindSetRightBit(IRQ0, Local0) Local0-- - Store(Local0, PRTE) + PRTE = Local0 } /* Status */ @@ -303,7 +303,7 @@ Device (LNKF) /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTF) + PRTF = 0x80 } /* Possible Resource Settings for this Link */ @@ -323,7 +323,7 @@ Device (LNKF) CreateWordField(RTLF, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = Zero /* Set the bit from PRTF */ ShiftLeft(1, And(PRTF, 0x0f), IRQ0) @@ -340,7 +340,7 @@ Device (LNKF) FindSetRightBit(IRQ0, Local0) Local0-- - Store(Local0, PRTF) + PRTF = Local0 } /* Status */ @@ -362,7 +362,7 @@ Device (LNKG) /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTG) + PRTG = 0x80 } /* Possible Resource Settings for this Link */ @@ -382,7 +382,7 @@ Device (LNKG) CreateWordField(RTLG, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = Zero /* Set the bit from PRTG */ ShiftLeft(1, And(PRTG, 0x0f), IRQ0) @@ -399,7 +399,7 @@ Device (LNKG) FindSetRightBit(IRQ0, Local0) Local0-- - Store(Local0, PRTG) + PRTG = Local0 } /* Status */ @@ -421,7 +421,7 @@ Device (LNKH) /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTH) + PRTH = 0x80 } /* Possible Resource Settings for this Link */ @@ -441,7 +441,7 @@ Device (LNKH) CreateWordField(RTLH, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = Zero /* Set the bit from PRTH */ ShiftLeft(1, And(PRTH, 0x0f), IRQ0) @@ -458,7 +458,7 @@ Device (LNKH) FindSetRightBit(IRQ0, Local0) Local0-- - Store(Local0, PRTH) + PRTH = Local0 } /* Status */ diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index fb61c533f5..904bc850ed 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -38,7 +38,7 @@ Device (LPCB) CreateDwordField (^RBUF, ^FBAR._BAS, FBAS) CreateDwordField (^RBUF, ^FBAR._LEN, FLEN) Local0 = CONFIG_COREBOOT_ROMSIZE_KB * 1024 - Store(Local0, FLEN) + FLEN = Local0 FBAS = 0xffffffff - Local0 + 1 Return (^RBUF) } diff --git a/src/soc/intel/braswell/acpi/lpe.asl b/src/soc/intel/braswell/acpi/lpe.asl index 629070bc61..02a88ff9e6 100644 --- a/src/soc/intel/braswell/acpi/lpe.asl +++ b/src/soc/intel/braswell/acpi/lpe.asl @@ -43,15 +43,15 @@ Device (LPEA) { /* Update BAR0 from NVS */ CreateDwordField (^RBUF, ^BAR0._BAS, BAS0) - Store (\LPB0, BAS0) + BAS0 = \LPB0 /* Update BAR1 from NVS */ CreateDwordField (^RBUF, ^BAR1._BAS, BAS1) - Store (\LPB1, BAS1) + BAS1 = \LPB1 /* Update LPE FW from NVS */ CreateDwordField (^RBUF, ^BAR2._BAS, BAS2) - Store (\LPFW, BAS2) + BAS2 = \LPFW /* Append any Mainboard defined GPIOs */ If (CondRefOf (^GBUF)) { diff --git a/src/soc/intel/braswell/acpi/lpss.asl b/src/soc/intel/braswell/acpi/lpss.asl index 09308e2541..b0477b24f7 100644 --- a/src/soc/intel/braswell/acpi/lpss.asl +++ b/src/soc/intel/braswell/acpi/lpss.asl @@ -49,7 +49,7 @@ Device (SDM1) Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S0B0, RBAS) + RBAS = \S0B0 Return (^RBUF) } @@ -81,7 +81,7 @@ Device (SDM2) Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S8B0, RBAS) + RBAS = \S8B0 Return (^RBUF) } @@ -121,7 +121,7 @@ Device (I2C1) Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S1B0, RBAS) + RBAS = \S1B0 Return (^RBUF) } @@ -180,7 +180,7 @@ Device (I2C2) Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S2B0, RBAS) + RBAS = \S2B0 Return (^RBUF) } @@ -239,7 +239,7 @@ Device (I2C3) Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S3B0, RBAS) + RBAS = \S3B0 Return (^RBUF) } @@ -298,7 +298,7 @@ Device (I2C4) Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S4B0, RBAS) + RBAS = \S4B0 Return (^RBUF) } @@ -357,7 +357,7 @@ Device (I2C5) Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S5B0, RBAS) + RBAS = \S5B0 Return (^RBUF) } @@ -416,7 +416,7 @@ Device (I2C6) Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S6B0, RBAS) + RBAS = \S6B0 Return (^RBUF) } @@ -475,7 +475,7 @@ Device (I2C7) Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S7B0, RBAS) + RBAS = \S7B0 Return (^RBUF) } @@ -528,7 +528,7 @@ Device (UAR1) Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\SCB0, RBAS) + RBAS = \SCB0 Return (^RBUF) } @@ -581,7 +581,7 @@ Device (UAR2) Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\SDB0, RBAS) + RBAS = \SDB0 Return (^RBUF) } diff --git a/src/soc/intel/braswell/acpi/scc.asl b/src/soc/intel/braswell/acpi/scc.asl index 44a0cbb017..36c49ed023 100644 --- a/src/soc/intel/braswell/acpi/scc.asl +++ b/src/soc/intel/braswell/acpi/scc.asl @@ -19,7 +19,7 @@ Device (EMMC) Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\C0B0, RBAS) + RBAS = \C0B0 Return (^RBUF) } @@ -120,7 +120,7 @@ Device (SDIO) Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\C1B0, RBAS) + RBAS = \C1B0 Return (^RBUF) } @@ -172,7 +172,7 @@ Device (SDCD) Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\C2B0, RBAS) + RBAS = \C2B0 Return (^RBUF) } diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index ade6441888..c8fcf0d33f 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -156,15 +156,15 @@ Method (_CRS, 0, Serialized) CreateDWordField (MCRS, LMEM._LEN, LLEN) If (LAnd (LPFW != Zero, LPEN == One)) { - Store (LPFW, LMIN) - Store (LMIN + 0x001FFFFF, LMAX) - Store (0x00200000, LLEN) + LMIN = LPFW + LMAX = LMIN + 0x001FFFFF + LLEN = 0x00200000 } Else { - Store (Zero, LMIN) - Store (Zero, LMAX) - Store (Zero, LLEN) + LMIN = Zero + LMAX = Zero + LLEN = Zero } /* Update PCI resource area */ @@ -173,8 +173,8 @@ Method (_CRS, 0, Serialized) CreateDwordField(MCRS, PMEM._LEN, PLEN) /* TOLM is BMBOUND accessible from IOSF so is saved in NVS */ - Store (\TOLM, PMIN) - Store (CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1, PMAX) + PMIN = \TOLM + PMAX = CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1 PLEN = PMAX - PMIN + 1 Return (MCRS) @@ -237,7 +237,7 @@ Device (IOSF) Method (_CRS) { CreateDwordField (^RBUF, ^RBAR._BAS, RBAS) - Store (CONFIG_ECAM_MMCONF_BASE_ADDRESS + 0xD0, RBAS) + RBAS = CONFIG_ECAM_MMCONF_BASE_ADDRESS + 0xD0 Return (^RBUF) } }