Documentation/soc/intel/icelake: Fix indentation in numbered list

Without this patch, the numbers restart at 1 at several points in the
HTML output.

Change-Id: Ie3634775ed9f993b1181785c58d72834183336e1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
This commit is contained in:
Jonathan Neuschäfer 2018-12-11 15:16:29 +01:00 committed by Patrick Georgi
parent afd40b2e2f
commit 84eb41d74c
1 changed files with 12 additions and 12 deletions

View File

@ -33,27 +33,27 @@ Like any other Intel SoC, Ice Lake coreboot development is also based on "Intel
## Create coreboot Image ## Create coreboot Image
1. Clone latest coreboot code as below 1. Clone latest coreboot code as below
```bash ```bash
$ git clone https://review.coreboot.org/coreboot.git $ git clone https://review.coreboot.org/coreboot.git
``` ```
2. Place blobs (ucode, me.bin and FSP packages) in appropriate locations 2. Place blobs (ucode, me.bin and FSP packages) in appropriate locations
Note: Note:
Consider the fact that ucode and ME kit for Ice Lake SoC will be available from Intel VIP site. Consider the fact that ucode and ME kit for Ice Lake SoC will be available from Intel VIP site.
After product launch, FSP binary will be available externally as any other program. After product launch, FSP binary will be available externally as any other program.
3. Create coreboot .config 3. Create coreboot .config
4. Build toolchain 4. Build toolchain
```bash ```bash
CPUS=$(nproc--ignore=1) make crossgcc-i386 iasl CPUS=$(nproc--ignore=1) make crossgcc-i386 iasl
``` ```
5. Build image 5. Build image
```bash ```bash
$ make # the image is generated as build/coreboot.rom $ make # the image is generated as build/coreboot.rom
``` ```
## Flashing coreboot ## Flashing coreboot