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sb/intel/lynxpoint: Use spaces around `|` 

Coding style says so.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I72386bbe4b38602a641bf8dc9448d6a3e95d297a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46718
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-24 11:53:47 +02:00 committed by Nico Huber
parent 2f30e8ca03
commit 84fa224b53
6 changed files with 10 additions and 10 deletions
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2
src/southbridge/intel/lynxpoint/early_pch.c
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@ -43,7 +43,7 @@ static void pch_enable_bars(void)
/* Enable ACPI BAR */
pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80);
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
/* Enable GPIO functionality. */
pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);

8
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -265,7 +265,7 @@ static void pch_power_options(struct device *dev)
/* Clear magic status bits to prevent unexpected wake */
reg32 = RCBA32(0x3310);
reg32 |= (1 << 4)|(1 << 5)|(1 << 0);
reg32 |= (1 << 4) | (1 << 5) | (1 << 0);
RCBA32(0x3310) = reg32;
reg16 = RCBA16(0x3f02);
@ -345,10 +345,10 @@ static void lpt_lp_pm_init(struct device *dev)
/* Set RCBA CIR28 0x3A84 based on SATA port enables */
data = 0x00001005;
/* Port 3 and 2 disabled */
if ((config->sata_port_map & ((1 << 3)|(1 << 2))) == 0)
if ((config->sata_port_map & ((1 << 3) | (1 << 2))) == 0)
data |= (1 << 24) | (1 << 26);
/* Port 1 and 0 disabled */
if ((config->sata_port_map & ((1 << 1)|(1 << 0))) == 0)
if ((config->sata_port_map & ((1 << 1) | (1 << 0))) == 0)
data |= (1 << 20) | (1 << 18);
RCBA32(0x3a84) = data;
@ -489,7 +489,7 @@ static void pch_fixups(struct device *dev)
* Enable DMI ASPM in the PCH
*/
RCBA32_AND_OR(0x2304, ~(1 << 10), 0);
RCBA32_OR(0x21a4, (1 << 11)|(1 << 10));
RCBA32_OR(0x21a4, (1 << 11) | (1 << 10));
RCBA32_OR(0x21a8, 0x3);
}

2
src/southbridge/intel/lynxpoint/serialio.c
View File

@ -119,7 +119,7 @@ static void serialio_init_once(int acpi_mode)
{
if (acpi_mode) {
/* Enable ACPI IRQ for IRQ13, IRQ7, IRQ6, IRQ5 in RCBA. */
RCBA32_OR(ACPIIRQEN, (1 << 13)|(1 << 7)|(1 << 6)|(1 << 5));
RCBA32_OR(ACPIIRQEN, (1 << 13) | (1 << 7) | (1 << 6) | (1 << 5));
}
/* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b. */

2
src/southbridge/intel/lynxpoint/smbus.c
View File

@ -17,7 +17,7 @@ static void pch_smbus_init(struct device *dev)
/* Enable clock gating */
/* FIXME: Using 32-bit ops with a 16-bit variable is a bug! These should be 16-bit! */
reg16 = pci_read_config32(dev, 0x80);
reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14));
reg16 &= ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14));
pci_write_config32(dev, 0x80, reg16);
/* Set Receive Slave Address */

2
src/southbridge/intel/lynxpoint/usb_ehci.c
View File

@ -119,7 +119,7 @@ void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ)
static void usb_ehci_clock_gating(struct device *dev)
{
/* IOBP 0xE5004001[7:6] = 11b */
pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6));
pch_iobp_update(0xe5004001, ~0, (1 << 7) | (1 << 6));
/* Dx:F0:DCh[5,2,1] = 111b
* Dx:F0:DCh[0] = 1b when EHCI controller is disabled */

4
src/southbridge/intel/lynxpoint/usb_xhci.c
View File

@ -235,7 +235,7 @@ static void usb_xhci_clock_gating(struct device *dev)
u32 reg32;
/* IOBP 0xE5004001[7:6] = 11b */
pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6));
pch_iobp_update(0xe5004001, ~0, (1 << 7) | (1 << 6));
reg32 = pci_read_config32(dev, 0x40);
reg32 &= ~(1 << 23); /* unsupported request */
@ -248,7 +248,7 @@ static void usb_xhci_clock_gating(struct device *dev)
reg32 |= (1 << 21) | (1 << 20);
} else {
/* D20:F0:40h[21,20,18,17,8] = 11111b */
reg32 |= (1 << 21)|(1 << 20)|(1 << 18)|(1 << 17)|(1 << 8);
reg32 |= (1 << 21) | (1 << 20) | (1 << 18) | (1 << 17) | (1 << 8);
}
/* Avoid writing upper byte as it is write-once */