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soc/intel/xeon_sp/Makefile.inc: Build EBG for SPR-SP 

Intel SPR-SP chipset has EBG instead of LBG.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I9429fe332bb5f01a41aa205c76ad9f0159f93eee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71959
Reviewed-by: Jian-Ming Wang <jianmingW@supermicro.com>
Reviewed-by: TimLiu-SMCI <timliu@supermicro.com.tw>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Chu 2022-12-13 12:11:45 +00:00 committed by Lean Sheng Tan
parent 3ed903fda9
commit 84fe84da84
1 changed files with 1 additions and 0 deletions
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src/soc/intel/xeon_sp/Makefile.inc
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@ -4,6 +4,7 @@ ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y)
subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx lbg subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx lbg
subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx lbg subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx lbg
subdirs-$(CONFIG_SOC_INTEL_SAPPHIRERAPIDS_SP) += spr ebg
bootblock-y += bootblock.c spi.c lpc.c pch.c bootblock-y += bootblock.c spi.c lpc.c pch.c
romstage-y += romstage.c reset.c util.c spi.c pmutil.c memmap.c romstage-y += romstage.c reset.c util.c spi.c pmutil.c memmap.c