Add support for DMP Vortex86EX PCI mainboard.
Change-Id: I8d42f765519e356d8f0cc6ed339d9b74f0a3e4d7 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3610 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Andrew Wu
Ronald G. Minnich
parent
f66dd6966a
commit
8522f9940a
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@ -50,6 +50,8 @@ config VENDOR_COMPAQ
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bool "Compaq"
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config VENDOR_DIGITALLOGIC
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bool "DIGITAL-LOGIC"
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config VENDOR_DMP
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bool "DMP"
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config VENDOR_EAGLELION
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bool "EagleLion"
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config VENDOR_ECS
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@ -160,6 +162,7 @@ source "src/mainboard/biostar/Kconfig"
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source "src/mainboard/broadcom/Kconfig"
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source "src/mainboard/compaq/Kconfig"
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source "src/mainboard/digitallogic/Kconfig"
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source "src/mainboard/dmp/Kconfig"
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source "src/mainboard/eaglelion/Kconfig"
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source "src/mainboard/ecs/Kconfig"
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source "src/mainboard/emulation/Kconfig"
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@ -0,0 +1,36 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 DMP Electronics Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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if VENDOR_DMP
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choice
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prompt "Mainboard model"
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config BOARD_DMP_EX
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bool "Vortex86EX"
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endchoice
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source "src/mainboard/dmp/vortex86ex/Kconfig"
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config MAINBOARD_VENDOR
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string
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default "DMP"
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endif # VENDOR_DMP
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,34 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 DMP Electronics Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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chip northbridge/dmp/vortex86ex # North Bridge
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device domain 0 on
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device pci 0.0 on end # Host Bridge
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chip southbridge/dmp/vortex86ex # South Bridge
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device pci 7.0 on end # ISA Bridge
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device pci 8.0 on end # Ethernet
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device pci a.0 on end # USB 1.1
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device pci a.1 on end # USB 2.0
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device pci b.0 on end # USB 1.1
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device pci b.1 on end # USB 2.0
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device pci c.0 on end # IDE
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end
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end # pci domain 0
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chip cpu/dmp/vortex86ex end # CPU
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end
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@ -0,0 +1,57 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 DMP Electronics Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/pirq_routing.h>
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static const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32 + 16 * 12, /* Max. number of devices on the bus */
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0x00, /* Interrupt router bus */
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(0x07 << 3) | 0x0, /* Interrupt router dev */
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0, /* IRQs devoted exclusively to PCI usage */
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0x17f3, /* Vendor */
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0x6031, /* Device */
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0, /* Miniport */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0xa, /* Checksum (has to be set to some value that
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* would give 0 after the sum of all bytes
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* for this structure (including checksum).
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*/
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{
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/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00, (0x01 << 3) | 0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x1, 0x0},
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{0x00, (0x02 << 3) | 0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x2, 0x0},
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{0x00, (0x03 << 3) | 0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x0, 0x0},
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{0x00, (0x04 << 3) | 0x0, {{0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}}, 0x4, 0x0},
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{0x00, (0x05 << 3) | 0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x5, 0x0},
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{0x00, (0x06 << 3) | 0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x6, 0x0},
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{0x00, (0x08 << 3) | 0x0, {{0x05, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
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{0x00, (0x0a << 3) | 0x0, {{0x07, 0xdef8}, {0x08, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
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{0x00, (0x0b << 3) | 0x0, {{0x09, 0xdef8}, {0x0a, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
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{0x00, (0x0c << 3) | 0x0, {{0x0b, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
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{0x00, (0x0f << 3) | 0x0, {{0x0d, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
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{0x00, (0x0e << 3) | 0x0, {{0x0e, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr, &intel_irq_routing_table);
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}
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@ -0,0 +1,34 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 DMP Electronics Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <boot/tables.h>
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#include <device/pci_def.h>
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static void mainboard_enable(device_t dev)
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{
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}
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struct chip_operations mainboard_ops = {
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CHIP_NAME("DMP VORTEX86EX Mainboard")
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.enable_dev = mainboard_enable,
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};
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@ -0,0 +1,360 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Andrew Wu <arw@dmp.com.tw>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdint.h>
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#include <arch/io.h>
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#include <stdlib.h>
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#include <console/console.h>
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#include "cpu/x86/mtrr/earlymtrr.c"
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#include "drivers/pc80/i8254.c"
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#include "northbridge/dmp/vortex86ex/northbridge.h"
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#include "southbridge/dmp/vortex86ex/southbridge.h"
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#include "northbridge/dmp/vortex86ex/raminit.c"
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#define DMP_CPUID_SX 0x31504d44
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#define DMP_CPUID_DX 0x32504d44
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#define DMP_CPUID_MX 0x33504d44
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#define DMP_CPUID_DX2 0x34504d44
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#define DMP_CPUID_MX_PLUS 0x35504d44
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#define DMP_CPUID_EX 0x37504d44
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/* Post codes */
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#define POST_DMP_ID_ERR 0x85
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#define POST_DRAM_TEST_ERR 0x86
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#define POST_DRAM_SIZING_ERR 0x77
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static u32 get_dmp_id(void)
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{
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return pci_read_config32(NB, NB_REG_CID);
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}
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/* Indirect access registers for Watch-dog timer, GPIO PORT 0,1
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* Index port is for I/O port 22h
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* Index port 13h (00: lock register, C5h: unlock register) for lock/unlock function
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* Index port 37h, 39h, 3Ah, 3Bh, 3Ch for Watchdog timer
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* Index port 46h, 47h, 4Ch, 4Dh, 4Eh, 4Fh for GPIO port 0, 1
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*/
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static void write_indirect_reg(u8 index, u8 data)
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{
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outb(index, 0x22);
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outb(data, 0x23);
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}
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static void lock_indirect_reg(void)
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{
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write_indirect_reg(0x13, 0x00);
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}
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static void unlock_indirect_reg(void)
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{
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write_indirect_reg(0x13, 0xc5);
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}
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static void disable_watchdog(void)
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{
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unlock_indirect_reg();
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// disable watchdog timer
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write_indirect_reg(0x37, 0x0);
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}
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void set_ex_powerdown_control(void)
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{
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u32 powerdown_ctrl;
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powerdown_ctrl = pci_read_config32(SB, 0xbc);
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#if CONFIG_TEMP_POWERDOWN
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powerdown_ctrl |= (1 << 31);
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#endif
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#if CONFIG_SATA_POWERDOWN
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powerdown_ctrl |= (1 << 30);
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#endif
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#if CONFIG_ADC_POWERDOWN
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powerdown_ctrl |= (1 << 28);
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#endif
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#if CONFIG_PCIE0_POWERDOWN
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powerdown_ctrl |= (1 << 13);
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#endif
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#if CONFIG_MAC_POWERDOWN
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powerdown_ctrl |= (1 << 3);
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#endif
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#if CONFIG_USB1_POWERDOWN
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powerdown_ctrl |= (1 << 1);
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#endif
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#if CONFIG_IDE_POWERDOWN
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powerdown_ctrl |= (1 << 0);
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#endif
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pci_write_config32(SB, 0xbc, powerdown_ctrl);
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}
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static void set_pci_nb_pmcr(void)
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{
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u8 pmcr = pci_read_config8(NB, NB_REG_PMCR);
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/*
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* Set PCI Master Max Cycle Length (MCL) to 32 PCI clocks.
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* Set PCI Master Burst Write Length (BL) to Burst length over 3.
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*/
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pmcr |= 0x0f;
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pci_write_config8(NB, NB_REG_PMCR, pmcr);
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}
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static void set_pci_sb_lpccr(void)
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{
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u8 lpccr = pci_read_config8(SB, SB_REG_LPCCR);
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/* Set PCI Soft Reset Control to 1.
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* (When the CPU soft reset is initialized, PCIRST# will be active.)
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* Set P92FE to 1. (I/O port 92 Register Write Function Enable.)
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* Set P92S to 1. (Internal Port 92h Selected.)
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*/
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lpccr |= 0x16;
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pci_write_config8(SB, SB_REG_LPCCR, lpccr);
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/* enable fast ga20 */
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outb(inb(SYSTEM_CTL_PORT) | 0x02, SYSTEM_CTL_PORT);
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}
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static u32 make_uart_config(u16 base, u8 irq)
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{
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/* Set base IO address only, skip IRQ. IRQ will be setup in
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* southbridge stage. */
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u32 cfg = 0;
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cfg |= 1 << 23; // UE = enabled.
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cfg |= base; // UIOA.
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return cfg;
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}
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#define SETUP_UART(n) \
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uart_cfg = make_uart_config(CONFIG_UART##n##_IO, CONFIG_UART##n##_IRQ);\
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outl(uart_cfg, 0xc00 + (n - 1) * 4);
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static void ex_uart_early_init(void)
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{
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#if CONFIG_TTYS0_BASE
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u32 uart_cfg = 0;
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/* Set UART Config I/O base address to 0xc00 */
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pci_write_config16(SB, 0x60, 0xc01);
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/* If serial console base address is defined, find out which
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* UART uses this address, and setup this UART first. */
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#if CONFIG_TTYS0_BASE == CONFIG_UART1_IO
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SETUP_UART(1)
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#elif CONFIG_TTYS0_BASE == CONFIG_UART2_IO
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SETUP_UART(2)
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#elif CONFIG_TTYS0_BASE == CONFIG_UART3_IO
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SETUP_UART(3)
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#elif CONFIG_TTYS0_BASE == CONFIG_UART4_IO
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SETUP_UART(4)
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#elif CONFIG_TTYS0_BASE == CONFIG_UART5_IO
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SETUP_UART(5)
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#elif CONFIG_TTYS0_BASE == CONFIG_UART6_IO
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SETUP_UART(6)
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#elif CONFIG_TTYS0_BASE == CONFIG_UART7_IO
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SETUP_UART(7)
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#elif CONFIG_TTYS0_BASE == CONFIG_UART8_IO
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SETUP_UART(8)
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#elif CONFIG_TTYS0_BASE == CONFIG_UART9_IO
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SETUP_UART(9)
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#elif CONFIG_TTYS0_BASE == CONFIG_UART10_IO
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SETUP_UART(10)
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#endif
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#endif
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}
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static void init_wdt1(void)
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{
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#if CONFIG_WDT1_INITIALIZE
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#if CONFIG_WDT1_ENABLE
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outb(0x1 << 6, 0xa8);
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#endif
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u8 wdt1_signal_reg = 0;
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#if CONFIG_WDT1_SINGAL_NMI
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wdt1_signal_reg = 0x0c << 4;
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#elif CONFIG_WDT1_SIGNAL_RESET
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wdt1_signal_reg = 0x0d << 4;
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#elif CONFIG_WDT1_SIGNAL_SMI
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wdt1_signal_reg = 0x0e << 4;
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#endif
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outb(wdt1_signal_reg, 0xa9);
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#endif
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}
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/* Fill 32bit pattern into specified DRAM region. */
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static void fill_dram(u32 * p, u32 pattern, u32 test_len)
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{
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if (test_len == 0)
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return;
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#if 0
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// C version, very slow.
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for (p = (u32 *) 0; (u32) p < test_len; p++) {
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*p = pattern;
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}
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#endif
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// ASM version, much faster.
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asm volatile (
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"cld\n\t"
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"rep\n\t"
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"stosl"
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: /* no output registers */
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: "c" (test_len / 4), "a" (pattern), "D" (p)
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);
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}
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/* Verify 32bit pattern in specified DRAM region.
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* Return -1 if ok, failed memory address if error. */
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static int verify_dram(u32 * p, u32 pattern, u32 test_len)
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{
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if (test_len == 0)
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return -1;
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#if 0
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// C version, very slow.
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for (p = (u32 *) 0; (u32) p < test_len; p++) {
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if (*p != pattern) {
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return (int)p;
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}
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}
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return -1;
|
||||
#endif
|
||||
u16 flags;
|
||||
int addr;
|
||||
asm volatile (
|
||||
"cld\n\t"
|
||||
"rep\n\t"
|
||||
"scasl\n\t"
|
||||
"lahf\n\t"
|
||||
: "=a" (flags), "=D" (addr)
|
||||
: "c" (test_len / 4), "a" (pattern), "D" (p)
|
||||
);
|
||||
if (flags & (1 << (6 + 8))) // x86 zero flag = bit 6.
|
||||
{
|
||||
return -1; // verify ok
|
||||
}
|
||||
return addr - 4; // verify error, return error address.
|
||||
}
|
||||
|
||||
static void test_dram_stability(void)
|
||||
{
|
||||
u32 test_len = 2048 * 1024;
|
||||
u32 pat = 0x5aa5a55a;
|
||||
u32 ext_mem_start = 0xc0000;
|
||||
u32 base_mem_test_len = test_len > 640 * 1024 ? 640 * 1024 : test_len;
|
||||
u32 ext_mem_test_len = test_len > ext_mem_start ? test_len - ext_mem_start : 0;
|
||||
if (ext_mem_test_len > 0) {
|
||||
/* Enable all shadow RAM region C0000 - FFFFF. */
|
||||
pci_write_config32(NB, NB_REG_MAR, 0x3ffffff0);
|
||||
}
|
||||
int v;
|
||||
fill_dram((u32 *) 0, pat, base_mem_test_len);
|
||||
fill_dram((u32 *) ext_mem_start, pat, ext_mem_test_len);
|
||||
v = verify_dram((u32 *) 0, pat, base_mem_test_len);
|
||||
if (v == -1) {
|
||||
v = verify_dram((u32 *) ext_mem_start, pat, ext_mem_test_len);
|
||||
}
|
||||
/* Change pattern and test again */
|
||||
if (v == -1) {
|
||||
pat = 0xa55a5aa5;
|
||||
fill_dram((u32 *) 0, pat, base_mem_test_len);
|
||||
fill_dram((u32 *) ext_mem_start, pat, ext_mem_test_len);
|
||||
v = verify_dram((u32 *) 0, pat, base_mem_test_len);
|
||||
if (v == -1) {
|
||||
v = verify_dram((u32 *) ext_mem_start, pat, ext_mem_test_len);
|
||||
}
|
||||
}
|
||||
if (v != -1) {
|
||||
post_code(POST_DRAM_TEST_ERR);
|
||||
print_emerg("DRAM stablility test error!\nADDR = ");
|
||||
print_emerg_hex32(v);
|
||||
print_emerg(", WRITE = ");
|
||||
print_emerg_hex32(pat);
|
||||
u32 r = *(u32 *) v;
|
||||
print_emerg(", READ = ");
|
||||
print_emerg_hex32(r);
|
||||
print_emerg(", XOR = ");
|
||||
print_emerg_hex32(r ^ pat);
|
||||
print_emerg("\n");
|
||||
die("System halted.\n");
|
||||
}
|
||||
if (ext_mem_test_len > 0) {
|
||||
/* Disable shadow RAM. */
|
||||
pci_write_config32(NB, NB_REG_MAR, 0x0);
|
||||
}
|
||||
}
|
||||
|
||||
static void enable_l2_cache(void)
|
||||
{
|
||||
/*
|
||||
* Enable L2 cache by setting PCI N/B function 1 L2 cache
|
||||
* control register (0xe8) bit 0 (L2_EN) and bit 1 (L2_WB_EN).
|
||||
*/
|
||||
u32 reg_nb_f1_e8;
|
||||
reg_nb_f1_e8 = pci_read_config8(NB1, 0xe8);
|
||||
reg_nb_f1_e8 |= 3;
|
||||
pci_write_config8(NB1, 0xe8, reg_nb_f1_e8);
|
||||
}
|
||||
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
device_t dev;
|
||||
u32 dmp_id;
|
||||
|
||||
dmp_id = get_dmp_id();
|
||||
if (dmp_id != DMP_CPUID_EX) {
|
||||
/* Not DMP Vortex86EX CPU. */
|
||||
post_code(POST_DMP_ID_ERR);
|
||||
while (1)
|
||||
hlt();
|
||||
}
|
||||
disable_watchdog();
|
||||
set_ex_powerdown_control();
|
||||
set_pci_nb_pmcr();
|
||||
set_pci_sb_lpccr();
|
||||
ex_uart_early_init();
|
||||
|
||||
console_init();
|
||||
|
||||
init_wdt1();
|
||||
|
||||
/* Initialize i8254 timers */
|
||||
post_code(0x42);
|
||||
setup_i8254();
|
||||
|
||||
/* Initialize DRAM */
|
||||
u8 reg_nb_f1_cc;
|
||||
/* Setup DDR3 Timing reg 0-3 / Config reg */
|
||||
pci_write_config16(NB, 0x6e, 0x0a2f);
|
||||
pci_write_config32(NB, 0x74, 0x84010200);
|
||||
pci_write_config32(NB, 0x78, 0x33405544);
|
||||
pci_write_config32(NB, 0x7c, 0x2e0f0e0b);
|
||||
/* Disable enhance read push write */
|
||||
reg_nb_f1_cc = pci_read_config8(NB1, 0xcc);
|
||||
reg_nb_f1_cc &= ~(1 << 4);
|
||||
pci_write_config8(NB1, 0xcc, reg_nb_f1_cc);
|
||||
if (detect_ddr3_dram_size()) {
|
||||
post_code(POST_DRAM_SIZING_ERR);
|
||||
die("DRAM sizing error!\n");
|
||||
}
|
||||
/* Reset enhance read push write to default(enable) */
|
||||
reg_nb_f1_cc |= (1 << 4);
|
||||
pci_write_config8(NB1, 0xcc, reg_nb_f1_cc);
|
||||
|
||||
print_ddr3_memory_setup();
|
||||
test_dram_stability();
|
||||
|
||||
/* CPU setup, romcc pukes on invd() */
|
||||
asm volatile ("invd");
|
||||
enable_cache();
|
||||
|
||||
enable_l2_cache();
|
||||
}
|
||||
Loading…
Reference in New Issue