copy_and_run.c is not needed twice, and it is used on non-car too.

So move it to src/arch/i386/lib/cbfs_and_run.c

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/arch/i386/lib/cbfs_and_run.c

@@ -40,3 +40,21 @@ void cbfs_and_run_core(const char *filename, unsigned ebp)
 		:: "a"(ebp), "D"(dst)
 	);
 }
+
+void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset);
+
+void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset)
+{
+	// FIXME fix input parameters instead normalizing them here.
+	if (cpu_reset == 1) cpu_reset = -1;
+	else cpu_reset = 0;
+
+	cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", cpu_reset);
+}
+
+#if CONFIG_AP_CODE_IN_CAR == 1
+static void __attribute__((regparm(0))) copy_and_run_ap_code_in_car(unsigned ret_addr)
+{
+	cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ap", ret_addr);
+}
+#endif

src/cpu/amd/car/copy_and_run.c

@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- * 
- * Copyright (C) 2009-2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-void cbfs_and_run_core(const char *filename, unsigned ebp);
-
-static void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset)
-{
-	cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", cpu_reset);
-}
-
-#if CONFIG_AP_CODE_IN_CAR == 1
-static void __attribute__((regparm(0))) copy_and_run_ap_code_in_car(unsigned ret_addr)
-{
-	cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ap", ret_addr);
-}
-#endif

src/cpu/intel/model_106cx/cache_as_ram_disable.c

@@ -17,7 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#include "cpu/x86/car/copy_and_run.c"
+
 
 /* called from assembler code */
 void stage1_main(unsigned long bist);

src/cpu/intel/model_6ex/cache_as_ram_disable.c

@@ -19,7 +19,7 @@
  * MA 02110-1301 USA
  */
 
-#include "cpu/x86/car/copy_and_run.c"
+
 
 /* called from assembler code */
 void stage1_main(unsigned long bist);

src/cpu/intel/model_6fx/cache_as_ram_disable.c

@@ -19,7 +19,7 @@
  * MA 02110-1301 USA
  */
 
-#include "cpu/x86/car/copy_and_run.c"
+
 
 void real_main(unsigned long bist);
 

src/cpu/x86/car/copy_and_run.c

@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- * 
- * Copyright (C) 2009-2010 coresystems GmbH
- * Written by Patrick Georgi <patrick.georgi@coresystems.de> 
- * for coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-void cbfs_and_run_core(const char *filename, unsigned ebp);
-
-static void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset)
-{
-	if (cpu_reset == 1) cpu_reset = -1;
-	else cpu_reset = 0;
-
-	cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", cpu_reset);
-}

src/mainboard/amd/dbm690t/romstage.c

@@ -88,7 +88,7 @@ static inline int spd_read_byte(u32 device, u32 address)
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

src/mainboard/amd/mahogany/romstage.c

@@ -88,7 +88,7 @@ static inline int spd_read_byte(u32 device, u32 address)
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

src/mainboard/amd/mahogany_fam10/romstage.c

@@ -99,7 +99,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "cpu/amd/model_10xxx/fidvid.c"

src/mainboard/amd/pistachio/romstage.c

@@ -82,7 +82,7 @@ static inline int spd_read_byte(u32 device, u32 address)
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

src/mainboard/amd/serengeti_cheetah/romstage.c

@@ -128,7 +128,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define DIMM6 0x56
 #define DIMM7 0x57
 
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

src/mainboard/amd/serengeti_cheetah_fam10/romstage.c

@@ -117,7 +117,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "cpu/amd/model_10xxx/fidvid.c"

src/mainboard/arima/hdama/romstage.c

@@ -86,7 +86,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define SECOND_CPU 1
 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/asrock/939a785gmh/romstage.c

@@ -93,7 +93,7 @@ static inline int spd_read_byte(u32 device, u32 address)
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

src/mainboard/asus/a8n_e/romstage.c

@@ -87,7 +87,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 

src/mainboard/asus/a8v-e_se/romstage.c

@@ -111,7 +111,7 @@ void soft_reset(void)
 #include "lib/generic_sdram.c"
 #include "cpu/amd/dualcore/dualcore.c"
 #include "southbridge/via/k8t890/k8t890_early_car.c"
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"

src/mainboard/asus/m2v-mx_se/romstage.c

@@ -96,7 +96,7 @@ void activate_spd_rom(const struct mem_controller *ctrl)
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "lib/generic_sdram.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 

src/mainboard/broadcom/blast/romstage.c

@@ -87,7 +87,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define DIMM2 0x52
 #define DIMM3 0x53
 
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

src/mainboard/gigabyte/ga_2761gxdk/romstage.c

@@ -134,7 +134,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "southbridge/sis/sis966/sis966_early_setup_ss.h"
 #include "southbridge/sis/sis966/sis966_early_setup_car.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/gigabyte/m57sli/romstage.c

@@ -132,7 +132,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/hp/dl145_g3/romstage.c

@@ -134,7 +134,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define DIMM6 0x56
 #define DIMM7 0x57
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/ibm/e325/romstage.c

@@ -83,7 +83,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define SECOND_CPU 1
 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/ibm/e326/romstage.c

@@ -83,7 +83,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define SECOND_CPU 1
 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/iwill/dk8_htx/romstage.c

@@ -113,7 +113,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define DIMM6 0x56
 #define DIMM7 0x57
 
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

src/mainboard/iwill/dk8s2/romstage.c

@@ -113,7 +113,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define DIMM6 0x56
 #define DIMM7 0x57
 
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

src/mainboard/iwill/dk8x/romstage.c

@@ -113,7 +113,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define DIMM6 0x56
 #define DIMM7 0x57
 
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

src/mainboard/kontron/kt690/romstage.c

@@ -89,7 +89,7 @@ static inline int spd_read_byte(u32 device, u32 address)
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

src/mainboard/msi/ms7135/romstage.c

@@ -89,7 +89,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 

src/mainboard/msi/ms7260/romstage.c

@@ -115,7 +115,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"

src/mainboard/msi/ms9185/romstage.c

@@ -129,7 +129,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define DIMM6 0x56
 #define DIMM7 0x57
 
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

src/mainboard/msi/ms9282/romstage.c

@@ -123,7 +123,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/msi/ms9652_fam10/romstage.c

@@ -122,7 +122,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/newisys/khepri/romstage.c

@@ -88,7 +88,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #endif
 #include "cpu/amd/dualcore/dualcore.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/nvidia/l1_2pvv/romstage.c

@@ -132,7 +132,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/sunw/ultra40/romstage.c

@@ -100,7 +100,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/supermicro/h8dme/romstage.c

@@ -175,7 +175,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/supermicro/h8dmr/romstage.c

@@ -120,7 +120,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/supermicro/h8dmr_fam10/romstage.c

@@ -111,7 +111,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/supermicro/h8qme_fam10/romstage.c

@@ -115,7 +115,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/technexion/tim5690/romstage.c

@@ -88,7 +88,7 @@ static inline int spd_read_byte(u32 device, u32 address)
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

src/mainboard/technexion/tim8690/romstage.c

@@ -88,7 +88,7 @@ static inline int spd_read_byte(u32 device, u32 address)
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

src/mainboard/tyan/s2735/romstage.c

@@ -63,7 +63,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/intel/e7501/reset_test.c"
 #include "lib/generic_sdram.c"
 
-#include "cpu/x86/car/copy_and_run.c"
+
 
 void stage1_main(unsigned long bist)
 {

src/mainboard/tyan/s2850/romstage.c

@@ -74,7 +74,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #endif
 #include "cpu/amd/dualcore/dualcore.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/tyan/s2875/romstage.c

@@ -76,7 +76,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #endif
 #include "cpu/amd/dualcore/dualcore.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/tyan/s2880/romstage.c

@@ -76,7 +76,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #endif
 #include "cpu/amd/dualcore/dualcore.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/tyan/s2881/romstage.c

@@ -76,7 +76,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/tyan/s2882/romstage.c

@@ -80,7 +80,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define SECOND_CPU 1
 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/tyan/s2885/romstage.c

@@ -78,7 +78,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #endif
 #include "cpu/amd/dualcore/dualcore.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/tyan/s2891/romstage.c

@@ -68,7 +68,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/tyan/s2892/romstage.c

@@ -72,7 +72,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/tyan/s2895/romstage.c

@@ -101,7 +101,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

src/mainboard/tyan/s2912/romstage.c

@@ -130,7 +130,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/tyan/s2912_fam10/romstage.c

@@ -121,7 +121,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/tyan/s4880/romstage.c

@@ -102,7 +102,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define DIMM2 0x52
 #define DIMM3 0x53
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/tyan/s4882/romstage.c

@@ -110,7 +110,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define DIMM2 0x52
 #define DIMM3 0x53
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

src/mainboard/via/epia-m700/romstage.c

@@ -47,7 +47,7 @@
 
 #include "northbridge/via/vx800/raminit.h"
 #include "northbridge/via/vx800/raminit.c"
-#include "cpu/x86/car/copy_and_run.c"
+
 #include "wakeup.h"
 
 #include "superio/winbond/w83697hf/w83697hf_early_serial.c"

src/mainboard/via/vt8454c/romstage.c

@@ -34,7 +34,7 @@
 
 #define DEACTIVATE_CAR 1
 #define DEACTIVATE_CAR_FILE "cpu/via/car/cache_as_ram_post.c"
-#include "cpu/x86/car/copy_and_run.c"
+
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "northbridge/via/cx700/cx700_early_smbus.c"

src/northbridge/via/vx800/examples/romstage.c

@@ -45,7 +45,7 @@
 
 #include "northbridge/via/vx800/raminit.h"
 #include "northbridge/via/vx800/raminit.c"
-#include "cpu/x86/car/copy_and_run.c"
+
 
 int acpi_is_wakeup_early_via_vx800(void)
 {