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amd/stoneyridge: Force PSP command reg settings in bootblock 

A subsequent patch to the PSP library will rely on the device already
having its PCI command register set to allow memory decoding and
mastering enabled.

Program the command register ahead of loading the SMU FW1 blob in
bootblock.  When the device has not been set up (e.g. when SMU FW
is not selectable), AGESA sets up the device.  As a result, a
similar change is not required before sending the DRAM ready
command.

Change-Id: Id586106751286c4767b5c16ed7e1604523635492
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22876
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marshall Dawson 2017-12-14 12:39:36 -07:00 committed by Martin Roth
parent f183a85932
commit 854d4dd9e2
1 changed files with 6 additions and 1 deletions
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7
src/soc/amd/stoneyridge/bootblock/bootblock.c
View File

@ -88,7 +88,7 @@ void bootblock_soc_early_init(void)
*/
static void load_smu_fw1(void)
{
u32 base, limit;
u32 base, limit, cmd;
/* Open a posted hole from 0x80000000 : 0xfed00000-1 */
base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE;
@ -100,6 +100,11 @@ static void load_smu_fw1(void)
pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE);
pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN);
/* Enable memory access and master */
cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND);
cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd);
psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw");
}