mb/google/brya/var/taeko: swap TPM i2c with TS i2c for the next build

Taeko is going to exchange i2c port for touchscreen and cr50.

BUG=b:211911780
TEST=build pass

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ib7273ba107c58e4cd90db00e301a399d7a7df76d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/mainboard/google/brya/Kconfig

@@ -87,7 +87,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x1 if BOARD_GOOGLE_REDRIX
 	default 0x3 if BOARD_GOOGLE_REDRIX4ES
 	default 0x1 if BOARD_GOOGLE_KANO
-	default 0x3 if BOARD_GOOGLE_TAEKO
+	default 0x1 if BOARD_GOOGLE_TAEKO
 	default 0x3 if BOARD_GOOGLE_TAEKO4ES
 	default 0x1 if BOARD_GOOGLE_FELWINTER
 	default 0x3 if BOARD_GOOGLE_ANAHERA

src/mainboard/google/brya/variants/taeko/gpio.c

@@ -140,10 +140,6 @@ static const struct pad_config override_gpio_table[] = {
 static const struct pad_config early_gpio_table[] = {
 	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
-	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
-	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
-	/* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
-	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
 	/*
 	 * D1  : ISH_GP1 ==> FP_RST_ODL
 	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
@@ -163,6 +159,10 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */

src/mainboard/google/brya/variants/taeko/overridetree.cb

@@ -79,11 +79,11 @@ chip soc/intel/alderlake
 	#+-------------------+---------------------------+
 	#| GSPI1             | Fingerprint MCU           |
 	#| I2C0              | Audio                     |
-	#| I2C1              | Touchscreen               |
+	#| I2C1              | cr50 TPM. Early init is   |
-	#| I2C2              | HPS                       |
-	#| I2C3              | cr50 TPM. Early init is   |
 	#|                   | required to set up a BAR  |
 	#|                   | for TPM communication     |
+	#| I2C2              | HPS                       |
+	#| I2C3              | Touchscreen               |
 	#| I2C5              | Trackpad                  |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
@@ -91,7 +91,11 @@ chip soc/intel/alderlake
 			.speed = I2C_SPEED_FAST,
 		},
 		.i2c[1] = {
+			.early_init = 1,
 			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 600,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
 		},
 		.i2c[2] = {
 			.speed = I2C_SPEED_FAST,
@@ -272,6 +276,28 @@ chip soc/intel/alderlake
 			end
 		end
 		device ref i2c1 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+				device i2c 50 on end
+			end
+		end
+		device ref i2c2 on
+			chip drivers/i2c/generic
+				register "hid" = ""GOOG0020""
+				register "desc" = ""Chrome OS HPS""
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)"  # EN_HPS_PWR
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)"  # HPS_INT_ODL
+				# HPS uses I2C addresses 0x30 and 0x51.
+				# The address we provide here is not significant because
+				# neither coreboot nor Linux have a driver for HPS,
+				# it's only used from userspace.
+				device i2c 30 on
+					probe HPS HPS_PRESENT
+				end
+			end
+		end
+		device ref i2c3 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""GDIX0000""
 				register "generic.desc" = ""Goodix Touchscreen""
@@ -312,28 +338,6 @@ chip soc/intel/alderlake
 				device i2c 10 on end
 			end
 		end
-		device ref i2c2 on
-			chip drivers/i2c/generic
-				register "hid" = ""GOOG0020""
-				register "desc" = ""Chrome OS HPS""
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)"  # EN_HPS_PWR
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)"  # HPS_INT_ODL
-				# HPS uses I2C addresses 0x30 and 0x51.
-				# The address we provide here is not significant because
-				# neither coreboot nor Linux have a driver for HPS,
-				# it's only used from userspace.
-				device i2c 30 on
-					probe HPS HPS_PRESENT
-				end
-			end
-		end
-		device ref i2c3 on
-			chip drivers/i2c/tpm
-				register "hid" = ""GOOG0005""
-				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
-				device i2c 50 on end
-			end
-		end
 		device ref i2c5 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""