From 85724170074994256ddb8a5fba65bca38d64777f Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Mon, 7 Feb 2022 14:34:08 +0800 Subject: [PATCH] mb/google/var/agah: Add gpios to lock Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that agah boots successfully to kernel. Signed-off-by: Eric Lai Change-Id: Ia9272f704e5656e6d0dc318dd1b51d50fc549839 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61658 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro Reviewed-by: Subrata Banik --- .../google/brya/variants/agah/gpio.c | 42 +++++++++---------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/src/mainboard/google/brya/variants/agah/gpio.c b/src/mainboard/google/brya/variants/agah/gpio.c index 25c20f3335..1423be91e4 100644 --- a/src/mainboard/google/brya/variants/agah/gpio.c +++ b/src/mainboard/google/brya/variants/agah/gpio.c @@ -29,17 +29,17 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_GPI(GPP_A22, NONE, DEEP), /* B3 : PROC_GP2 ==> GPU_PERST_L */ - PAD_CFG_GPO(GPP_B3, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_B3, 1, LOCK_CONFIG), /* B5 : ISH_I2C0_SDA ==> PCH_I2C_NVDD_GPU_SDA */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG), /* B6 : ISH_I2C0_SDA ==> PCH_I2C_NVDD_GPU_SCL */ - PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */ PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ - PAD_NC(GPP_B15, NONE), + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), /* C0 : SMBCLK ==> NC */ PAD_NC(GPP_C0, NONE), @@ -55,25 +55,25 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_C7, NONE), /* D0 : ISH_GP0 ==> NC */ - PAD_NC(GPP_D0, NONE), + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), /* D1 : ISH_GP1 ==> NC */ - PAD_NC(GPP_D1, NONE), + PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG), /* D2 : ISH_GP2 ==> LAN_PR_ISOLATE_ODL */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG), /* D3 : ISH_GP3 ==> NC */ - PAD_NC(GPP_D3, NONE), + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), /* D5 : SRCCLKREQ0# ==> GPU_CLKREQ_ODL */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* D9 : ISH_SPI_CS# ==> GPU_THERM_INT_ODL */ - PAD_CFG_GPI(GPP_D9, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_D9, NONE, LOCK_CONFIG), /* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */ - PAD_NC(GPP_D10, NONE), + PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_NC(GPP_D13, NONE), + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_NC(GPP_D15, NONE), + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_NC(GPP_D16, NONE), + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), /* E0 : SATAXPCIE0 ==> EN_PPVAR_GPU_NVVDD_X_OD */ PAD_CFG_GPO(GPP_E0, 0, DEEP), @@ -86,13 +86,13 @@ static const struct pad_config override_gpio_table[] = { /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), /* E9 : USB_OC0# ==> USB_A2_OC_ODL */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG), /* E10 : THC0_SPI1_CS# ==> EN_PP0950_GPU_X */ - PAD_CFG_GPO(GPP_E10, 0, DEEP), + PAD_CFG_GPO_LOCK(GPP_E10, 0, LOCK_CONFIG), /* E16 : RSVD_TP ==> PG_PPVAR_GPU_NVVDD_X_OD */ PAD_CFG_GPO(GPP_E16, 0, DEEP), /* E17 : RSVD_TP ==> PG_PP0950_GPU_X_OD */ - PAD_CFG_GPI(GPP_E17, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_E17, NONE, LOCK_CONFIG), /* E18 : DDP1_CTRLCLK ==> EN_PP1800_GPU_X */ PAD_CFG_GPO(GPP_E18, 0, DEEP), /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ @@ -105,15 +105,15 @@ static const struct pad_config override_gpio_table[] = { /* F6 : CNV_PA_BLANKING ==> NC */ PAD_NC(GPP_F6, NONE), /* F11 : THC1_SPI2_CLK ==> NC */ - PAD_NC(GPP_F11, NONE), + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), /* F12 : GSXDOUT ==> NC */ - PAD_NC(GPP_F12, NONE), + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), /* F13 : GSXDOUT ==> NC */ - PAD_NC(GPP_F13, NONE), + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), /* F15 : GSXSRESET# ==> NC */ - PAD_NC(GPP_F15, NONE), + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), /* F16 : GSXCLK ==> NC */ - PAD_NC(GPP_F16, NONE), + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), /* F19 : SRCCLKREQ6# ==> NC */ PAD_NC(GPP_F19, NONE), /* F20 : EXT_PWR_GATE# ==> NC */