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soc/mediatek/mt8192: mt6315: update initial flow 

We saw EXT_PMIC_EN1 and PPVAR_DVDD_PROC_BC power off sequence
failure, and after checking MT6315 MT6315 PMIC protection key
summary.xlsx and MT6315 Top and CLK programming guide.docx,
we found there are something wrong about the sequence of magic
key protection flow and clk setting. Update correct initial
flow.

BUG=b:179000151
BRANCH=none
TEST=boot asurada correctly

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I1b7f970a44904fda09a97f4064eef7c95feefad7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51245
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Hsin-Hsiung Wang 2021-03-04 10:49:14 +08:00 committed by Hung-Te Lin
parent 670cd9719e
commit 8579f23353
2 changed files with 20 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
src/soc/mediatek/mt8192/mt6315.c
View File

@ -91,16 +91,16 @@ static const struct mt6315_setting init_setting_cpu[] = {
{0x16AD, 0x81, 0xFF, 0},
{0x16AE, 0x13, 0x3F, 0},
/* enable magic key protection */
{0x3A9, 0, 0xFF, 0},
{0x3A8, 0, 0xFF, 0},
{0x3A0, 0, 0xFF, 0},
{0x39F, 0, 0xFF, 0},
{0x993, 0, 0xFF, 0},
{0x992, 0, 0xFF, 0},
{0x1418, 0, 0xFF, 0},
{0x3A1, 0, 0xFF, 0},
{0x3A2, 0, 0xFF, 0},
{0x1417, 0, 0xFF, 0},
{0x3a2, 0, 0xFF, 0},
{0x3a1, 0, 0xFF, 0},
{0x1418, 0, 0xFF, 0},
{0x992, 0, 0xFF, 0},
{0x993, 0, 0xFF, 0},
{0x39F, 0, 0xFF, 0},
{0x3A0, 0, 0xFF, 0},
{0x3A8, 0, 0xFF, 0},
{0x3A9, 0, 0xFF, 0},
};
static const struct mt6315_setting init_setting_gpu[] = {
@ -183,16 +183,16 @@ static const struct mt6315_setting init_setting_gpu[] = {
/* Don't remove this! it's MT6315 for GPU only to disable VBUCK3 */
{0x1440, 0x0, 0x4, 0},
/* enable magic key protection */
{0x3A9, 0, 0xFF, 0},
{0x3A8, 0, 0xFF, 0},
{0x3A0, 0, 0xFF, 0},
{0x39F, 0, 0xFF, 0},
{0x993, 0, 0xFF, 0},
{0x992, 0, 0xFF, 0},
{0x1418, 0, 0xFF, 0},
{0x3A1, 0, 0xFF, 0},
{0x3A2, 0, 0xFF, 0},
{0x1417, 0, 0xFF, 0},
{0x3a2, 0, 0xFF, 0},
{0x3a1, 0, 0xFF, 0},
{0x1418, 0, 0xFF, 0},
{0x992, 0, 0xFF, 0},
{0x993, 0, 0xFF, 0},
{0x39F, 0, 0xFF, 0},
{0x3A0, 0, 0xFF, 0},
{0x3A8, 0, 0xFF, 0},
{0x3A9, 0, 0xFF, 0},
};
static void mt6315_read(u32 slvid, u32 reg, u32 *data)
@ -219,8 +219,8 @@ static void mt6315_wdt_enable(u32 slvid)
mt6315_write(slvid, 0x127, 0x8);
udelay(50);
mt6315_write(slvid, 0x128, 0x8);
mt6315_write(slvid, 0x3A9, 0);
mt6315_write(slvid, 0x3A8, 0);
mt6315_write(slvid, 0x3A9, 0);
}
static void mt6315_init_setting(void)

2
src/soc/mediatek/mt8192/pmif_spmi.c
View File

@ -61,7 +61,7 @@ static int spmi_config_master(void)
/* Software reset */
SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 1, UNLOCK_KEY, 0x85);
SET32_BITFIELDS(&mtk_topckgen->clk_cfg_15,
SET32_BITFIELDS(&mtk_topckgen->clk_cfg_15_clr,
CLK_SPMI_MST_SEL, 0x7,
CLK_SPMI_MST_INT, 1,
PDN_SPMI_MST, 1);