mb/google/corsola: Configure TPM

Initialize SPI bus 2 for TPM control.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I8ede68d6eb594890195e8464151c1c0f88aeee43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

src/mainboard/google/corsola/Kconfig

@@ -24,6 +24,8 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_SPI
+	select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT
+	select MAINBOARD_HAS_TPM2 if VBOOT
 
 config MAINBOARD_DIR
 	string
@@ -43,6 +45,10 @@ config SDCARD_INIT
 	bool
 	default n
 
+config DRIVER_TPM_SPI_BUS
+	hex
+	default 0x2
+
 config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
 	default 0x1

src/mainboard/google/corsola/bootblock.c

@@ -9,6 +9,8 @@
 void bootblock_mainboard_init(void)
 {
 	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
+	mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
 	mtk_snfc_init(SPI_NOR_GPIO_SET0);
 	setup_chromeos_gpios();
+	gpio_eint_configure(GPIO_GSC_AP_INT, IRQ_TYPE_EDGE_RISING);
 }

src/mainboard/google/corsola/chromeos.c

@@ -3,6 +3,7 @@
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <gpio.h>
+#include <security/tpm/tis.h>
 
 #include "gpio.h"
 
@@ -32,3 +33,8 @@ int get_ec_is_trusted(void)
 	/* EC is trusted if not in RW. This is active low. */
 	return !!gpio_get(GPIO_EC_IN_RW);
 }
+
+int tis_plat_irq_status(void)
+{
+	return gpio_eint_poll(GPIO_GSC_AP_INT);
+}