intel/skylake: Refactor IRQ assignments
When creating the IRQ routing, referenced device and function number are always of the same PCI device. Change-Id: Ifc4795245187f8d70650242a56e6ce771ef2167a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35735 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
parent
0b4298c242
commit
85b6c66c83
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@ -31,11 +31,11 @@
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#define PCH_PHRC 7
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#define PCH_MAX_IRQ_CONFIG 8
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#define DEVICE_INT_CONFIG(dev, func, line, irqno) {\
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.Device = dev, \
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.Function = func, \
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.IntX = line, \
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.Irq = irqno }
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#define DEVICE_INT_CONFIG(devfn, line, irqno) {\
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.Device = PCI_SLOT(devfn), \
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.Function = PCI_FUNC(devfn), \
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.IntX = (line), \
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.Irq = (irqno) }
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#define no_int 0
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#define int_A 1
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@ -28,194 +28,152 @@ static const SI_PCH_DEVICE_INTERRUPT_CONFIG devintconfig[] = {
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* cAVS(Audio, Voice, Speech), INTA is default, programmed in
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* PciCfgSpace 3Dh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC,
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PCI_FUNC(PCH_DEVFN_HDA), int_A, cAVS_INTA_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_HDA, int_A, cAVS_INTA_IRQ),
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/*
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* SMBus Controller, no default value, programmed in
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* PciCfgSpace 3Dh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC,
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PCI_FUNC(PCH_DEVFN_SMBUS), int_A, SMBUS_INTA_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_SMBUS, int_A, SMBUS_INTA_IRQ),
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/* GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC,
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PCI_FUNC(PCH_DEVFN_GBE), int_A, GbE_INTA_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_GBE, int_A, GbE_INTA_IRQ),
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/* TraceHub, INTA is default, RO register */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC,
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PCI_FUNC(PCH_DEVFN_TRACEHUB), int_A,
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TRACE_HUB_INTA_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_TRACEHUB, int_A, TRACE_HUB_INTA_IRQ),
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/*
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* SerialIo: UART #0, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[7]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
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PCI_FUNC(PCH_DEVFN_UART0), int_A, LPSS_UART0_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_UART0, int_A, LPSS_UART0_IRQ),
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/*
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* SerialIo: UART #1, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[8]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
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PCI_FUNC(PCH_DEVFN_UART1), int_B, LPSS_UART1_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_UART1, int_B, LPSS_UART1_IRQ),
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/*
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* SerialIo: SPI #0, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[10]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
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PCI_FUNC(PCH_DEVFN_GSPI0), int_C, LPSS_SPI0_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_GSPI0, int_C, LPSS_SPI0_IRQ),
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/*
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* SerialIo: SPI #1, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[11]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
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PCI_FUNC(PCH_DEVFN_GSPI1), int_D, LPSS_SPI1_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_GSPI1, int_D, LPSS_SPI1_IRQ),
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/* SCS: eMMC (SKL PCH-LP Only) */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
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PCI_FUNC(PCH_DEVFN_EMMC), int_B, eMMC_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_EMMC, int_B, eMMC_IRQ),
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/* SCS: SDIO (SKL PCH-LP Only) */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
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PCI_FUNC(PCH_DEVFN_SDIO), int_C, SDIO_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_SDIO, int_C, SDIO_IRQ),
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/* SCS: SDCard (SKL PCH-LP Only) */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
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PCI_FUNC(PCH_DEVFN_SDCARD), int_D, SD_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_SDCARD, int_D, SD_IRQ),
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/* PCI Express Port, INT is default,
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* programmed in PciCfgSpace + FCh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1,
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PCI_FUNC(PCH_DEVFN_PCIE9), int_A, PCIE_9_IRQ),
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1,
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PCI_FUNC(PCH_DEVFN_PCIE10), int_B, PCIE_10_IRQ),
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1,
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PCI_FUNC(PCH_DEVFN_PCIE11), int_C, PCIE_11_IRQ),
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1,
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PCI_FUNC(PCH_DEVFN_PCIE12), int_D, PCIE_12_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_PCIE9, int_A, PCIE_9_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_PCIE10, int_B, PCIE_10_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_PCIE11, int_C, PCIE_11_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_PCIE12, int_D, PCIE_12_IRQ),
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/*
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* PCI Express Port 1, INT is default,
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* programmed in PciCfgSpace + FCh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
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PCI_FUNC(PCH_DEVFN_PCIE1), int_A, PCIE_1_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_PCIE1, int_A, PCIE_1_IRQ),
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/*
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* PCI Express Port 2, INT is default,
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* programmed in PciCfgSpace + FCh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
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PCI_FUNC(PCH_DEVFN_PCIE2), int_B, PCIE_2_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_PCIE2, int_B, PCIE_2_IRQ),
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/*
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* PCI Express Port 3, INT is default,
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* programmed in PciCfgSpace + FCh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
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PCI_FUNC(PCH_DEVFN_PCIE3), int_C, PCIE_3_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_PCIE3, int_C, PCIE_3_IRQ),
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/*
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* PCI Express Port 4, INT is default,
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* programmed in PciCfgSpace + FCh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
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PCI_FUNC(PCH_DEVFN_PCIE4), int_D, PCIE_4_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_PCIE4, int_D, PCIE_4_IRQ),
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/*
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* PCI Express Port 5, INT is default,
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* programmed in PciCfgSpace + FCh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
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PCI_FUNC(PCH_DEVFN_PCIE5), int_A, PCIE_5_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_PCIE5, int_A, PCIE_5_IRQ),
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/*
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* PCI Express Port 6, INT is default,
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* programmed in PciCfgSpace + FCh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
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PCI_FUNC(PCH_DEVFN_PCIE6), int_B, PCIE_6_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_PCIE6, int_B, PCIE_6_IRQ),
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/*
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* PCI Express Port 7, INT is default,
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* programmed in PciCfgSpace + FCh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
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PCI_FUNC(PCH_DEVFN_PCIE7), int_C, PCIE_7_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_PCIE7, int_C, PCIE_7_IRQ),
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/*
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* PCI Express Port 8, INT is default,
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* programmed in PciCfgSpace + FCh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
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PCI_FUNC(PCH_DEVFN_PCIE8), int_D, PCIE_8_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_PCIE8, int_D, PCIE_8_IRQ),
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/*
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* SerialIo UART Controller #2, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[9]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2,
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PCI_FUNC(PCH_DEVFN_UART2), int_A, LPSS_UART2_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_UART2, int_A, LPSS_UART2_IRQ),
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/*
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* SerialIo UART Controller #5, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[6]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2,
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PCI_FUNC(PCH_DEVFN_I2C5), int_B, LPSS_I2C5_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_I2C5, int_B, LPSS_I2C5_IRQ),
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/*
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* SerialIo UART Controller #4, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[5]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2,
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PCI_FUNC(PCH_DEVFN_I2C4), int_C, LPSS_I2C4_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_I2C4, int_C, LPSS_I2C4_IRQ),
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/*
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* SATA Controller, INTA is default,
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* programmed in PciCfgSpace + 3Dh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_SATA,
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PCI_FUNC(PCH_DEVFN_SATA), int_A, SATA_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_SATA, int_A, SATA_IRQ),
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/* CSME: HECI #1 */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE,
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PCI_FUNC(PCH_DEVFN_CSE), int_A, HECI_1_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_CSE, int_A, HECI_1_IRQ),
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/* CSME: HECI #2 */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE,
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PCI_FUNC(PCH_DEVFN_CSE_2), int_B, HECI_2_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_CSE_2, int_B, HECI_2_IRQ),
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/* CSME: IDE-Redirection (IDE-R) */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE,
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PCI_FUNC(PCH_DEVFN_CSE_IDER), int_C, IDER_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_CSE_IDER, int_C, IDER_IRQ),
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/* CSME: Keyboard and Text (KT) Redirection */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE,
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PCI_FUNC(PCH_DEVFN_CSE_KT), int_D, KT_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_CSE_KT, int_D, KT_IRQ),
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/* CSME: HECI #3 */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE,
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PCI_FUNC(PCH_DEVFN_CSE_3), int_A, HECI_3_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_CSE_3, int_A, HECI_3_IRQ),
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/*
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* SerialIo I2C Controller #0, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[1]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1,
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PCI_FUNC(PCH_DEVFN_I2C0), int_A, LPSS_I2C0_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_I2C0, int_A, LPSS_I2C0_IRQ),
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/*
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* SerialIo I2C Controller #1, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[2]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1,
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PCI_FUNC(PCH_DEVFN_I2C1), int_B, LPSS_I2C1_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_I2C1, int_B, LPSS_I2C1_IRQ),
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/*
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* SerialIo I2C Controller #2, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[3]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1,
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PCI_FUNC(PCH_DEVFN_I2C2), int_C, LPSS_I2C2_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_I2C2, int_C, LPSS_I2C2_IRQ),
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/*
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* SerialIo I2C Controller #3, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[4]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1,
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PCI_FUNC(PCH_DEVFN_I2C3), int_D, LPSS_I2C3_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_I2C3, int_D, LPSS_I2C3_IRQ),
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/*
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* USB 3.0 xHCI Controller, no default value,
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* programmed in PciCfgSpace 3Dh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI,
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PCI_FUNC(PCH_DEVFN_XHCI), int_A, XHCI_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_XHCI, int_A, XHCI_IRQ),
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/* USB Device Controller (OTG) */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI,
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PCI_FUNC(PCH_DEVFN_USBOTG), int_B, OTG_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_USBOTG, int_B, OTG_IRQ),
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/* Thermal Subsystem */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI,
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PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THERMAL_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_THERMAL, int_C, THERMAL_IRQ),
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/* Camera IO Host Controller */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI,
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PCI_FUNC(PCH_DEVFN_CIO), int_A, CIO_INTA_IRQ),
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DEVICE_INT_CONFIG(PCH_DEVFN_CIO, int_A, CIO_INTA_IRQ),
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/* Integrated Sensor Hub */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH,
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PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ)
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DEVICE_INT_CONFIG(PCH_DEVFN_ISH, int_A, ISH_IRQ)
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};
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void soc_irq_settings(FSP_SIL_UPD *params)
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