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intel/skylake: Refactor IRQ assignments 

When creating the IRQ routing, referenced device and
function number are always of the same PCI device.

Change-Id: Ifc4795245187f8d70650242a56e6ce771ef2167a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35735
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-09-30 22:40:53 +03:00
parent 0b4298c242
commit 85b6c66c83
2 changed files with 46 additions and 88 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/soc/intel/skylake/include/soc/interrupt.h
View File

@ -31,11 +31,11 @@
#define PCH_PHRC 7 #define PCH_PHRC 7
#define PCH_MAX_IRQ_CONFIG 8 #define PCH_MAX_IRQ_CONFIG 8
#define DEVICE_INT_CONFIG(dev, func, line, irqno) {\ #define DEVICE_INT_CONFIG(devfn, line, irqno) {\
.Device = dev, \ .Device = PCI_SLOT(devfn), \
.Function = func, \ .Function = PCI_FUNC(devfn), \
.IntX = line, \ .IntX = (line), \
.Irq = irqno } .Irq = (irqno) }
#define no_int 0 #define no_int 0
#define int_A 1 #define int_A 1

124
src/soc/intel/skylake/irq.c
View File

@ -28,194 +28,152 @@ static const SI_PCH_DEVICE_INTERRUPT_CONFIG devintconfig[] = {
* cAVS(Audio, Voice, Speech), INTA is default, programmed in * cAVS(Audio, Voice, Speech), INTA is default, programmed in
* PciCfgSpace 3Dh * PciCfgSpace 3Dh
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, DEVICE_INT_CONFIG(PCH_DEVFN_HDA, int_A, cAVS_INTA_IRQ),
PCI_FUNC(PCH_DEVFN_HDA), int_A, cAVS_INTA_IRQ),
/* /*
* SMBus Controller, no default value, programmed in * SMBus Controller, no default value, programmed in
* PciCfgSpace 3Dh * PciCfgSpace 3Dh
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, DEVICE_INT_CONFIG(PCH_DEVFN_SMBUS, int_A, SMBUS_INTA_IRQ),
PCI_FUNC(PCH_DEVFN_SMBUS), int_A, SMBUS_INTA_IRQ),
/* GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh */ /* GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, DEVICE_INT_CONFIG(PCH_DEVFN_GBE, int_A, GbE_INTA_IRQ),
PCI_FUNC(PCH_DEVFN_GBE), int_A, GbE_INTA_IRQ),
/* TraceHub, INTA is default, RO register */ /* TraceHub, INTA is default, RO register */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, DEVICE_INT_CONFIG(PCH_DEVFN_TRACEHUB, int_A, TRACE_HUB_INTA_IRQ),
PCI_FUNC(PCH_DEVFN_TRACEHUB), int_A,
TRACE_HUB_INTA_IRQ),
/* /*
* SerialIo: UART #0, INTA is default, * SerialIo: UART #0, INTA is default,
* programmed in PCR[SERIALIO] + PCICFGCTRL[7] * programmed in PCR[SERIALIO] + PCICFGCTRL[7]
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, DEVICE_INT_CONFIG(PCH_DEVFN_UART0, int_A, LPSS_UART0_IRQ),
PCI_FUNC(PCH_DEVFN_UART0), int_A, LPSS_UART0_IRQ),
/* /*
* SerialIo: UART #1, INTA is default, * SerialIo: UART #1, INTA is default,
* programmed in PCR[SERIALIO] + PCICFGCTRL[8] * programmed in PCR[SERIALIO] + PCICFGCTRL[8]
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, DEVICE_INT_CONFIG(PCH_DEVFN_UART1, int_B, LPSS_UART1_IRQ),
PCI_FUNC(PCH_DEVFN_UART1), int_B, LPSS_UART1_IRQ),
/* /*
* SerialIo: SPI #0, INTA is default, * SerialIo: SPI #0, INTA is default,
* programmed in PCR[SERIALIO] + PCICFGCTRL[10] * programmed in PCR[SERIALIO] + PCICFGCTRL[10]
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, DEVICE_INT_CONFIG(PCH_DEVFN_GSPI0, int_C, LPSS_SPI0_IRQ),
PCI_FUNC(PCH_DEVFN_GSPI0), int_C, LPSS_SPI0_IRQ),
/* /*
* SerialIo: SPI #1, INTA is default, * SerialIo: SPI #1, INTA is default,
* programmed in PCR[SERIALIO] + PCICFGCTRL[11] * programmed in PCR[SERIALIO] + PCICFGCTRL[11]
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, DEVICE_INT_CONFIG(PCH_DEVFN_GSPI1, int_D, LPSS_SPI1_IRQ),
PCI_FUNC(PCH_DEVFN_GSPI1), int_D, LPSS_SPI1_IRQ),
/* SCS: eMMC (SKL PCH-LP Only) */ /* SCS: eMMC (SKL PCH-LP Only) */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, DEVICE_INT_CONFIG(PCH_DEVFN_EMMC, int_B, eMMC_IRQ),
PCI_FUNC(PCH_DEVFN_EMMC), int_B, eMMC_IRQ),
/* SCS: SDIO (SKL PCH-LP Only) */ /* SCS: SDIO (SKL PCH-LP Only) */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, DEVICE_INT_CONFIG(PCH_DEVFN_SDIO, int_C, SDIO_IRQ),
PCI_FUNC(PCH_DEVFN_SDIO), int_C, SDIO_IRQ),
/* SCS: SDCard (SKL PCH-LP Only) */ /* SCS: SDCard (SKL PCH-LP Only) */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, DEVICE_INT_CONFIG(PCH_DEVFN_SDCARD, int_D, SD_IRQ),
PCI_FUNC(PCH_DEVFN_SDCARD), int_D, SD_IRQ),
/* PCI Express Port, INT is default, /* PCI Express Port, INT is default,
* programmed in PciCfgSpace + FCh * programmed in PciCfgSpace + FCh
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, DEVICE_INT_CONFIG(PCH_DEVFN_PCIE9, int_A, PCIE_9_IRQ),
PCI_FUNC(PCH_DEVFN_PCIE9), int_A, PCIE_9_IRQ), DEVICE_INT_CONFIG(PCH_DEVFN_PCIE10, int_B, PCIE_10_IRQ),
DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, DEVICE_INT_CONFIG(PCH_DEVFN_PCIE11, int_C, PCIE_11_IRQ),
PCI_FUNC(PCH_DEVFN_PCIE10), int_B, PCIE_10_IRQ), DEVICE_INT_CONFIG(PCH_DEVFN_PCIE12, int_D, PCIE_12_IRQ),
DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1,
PCI_FUNC(PCH_DEVFN_PCIE11), int_C, PCIE_11_IRQ),
DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1,
PCI_FUNC(PCH_DEVFN_PCIE12), int_D, PCIE_12_IRQ),
/* /*
* PCI Express Port 1, INT is default, * PCI Express Port 1, INT is default,
* programmed in PciCfgSpace + FCh * programmed in PciCfgSpace + FCh
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, DEVICE_INT_CONFIG(PCH_DEVFN_PCIE1, int_A, PCIE_1_IRQ),
PCI_FUNC(PCH_DEVFN_PCIE1), int_A, PCIE_1_IRQ),
/* /*
* PCI Express Port 2, INT is default, * PCI Express Port 2, INT is default,
* programmed in PciCfgSpace + FCh * programmed in PciCfgSpace + FCh
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, DEVICE_INT_CONFIG(PCH_DEVFN_PCIE2, int_B, PCIE_2_IRQ),
PCI_FUNC(PCH_DEVFN_PCIE2), int_B, PCIE_2_IRQ),
/* /*
* PCI Express Port 3, INT is default, * PCI Express Port 3, INT is default,
* programmed in PciCfgSpace + FCh * programmed in PciCfgSpace + FCh
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, DEVICE_INT_CONFIG(PCH_DEVFN_PCIE3, int_C, PCIE_3_IRQ),
PCI_FUNC(PCH_DEVFN_PCIE3), int_C, PCIE_3_IRQ),
/* /*
* PCI Express Port 4, INT is default, * PCI Express Port 4, INT is default,
* programmed in PciCfgSpace + FCh * programmed in PciCfgSpace + FCh
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, DEVICE_INT_CONFIG(PCH_DEVFN_PCIE4, int_D, PCIE_4_IRQ),
PCI_FUNC(PCH_DEVFN_PCIE4), int_D, PCIE_4_IRQ),
/* /*
* PCI Express Port 5, INT is default, * PCI Express Port 5, INT is default,
* programmed in PciCfgSpace + FCh * programmed in PciCfgSpace + FCh
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, DEVICE_INT_CONFIG(PCH_DEVFN_PCIE5, int_A, PCIE_5_IRQ),
PCI_FUNC(PCH_DEVFN_PCIE5), int_A, PCIE_5_IRQ),
/* /*
* PCI Express Port 6, INT is default, * PCI Express Port 6, INT is default,
* programmed in PciCfgSpace + FCh * programmed in PciCfgSpace + FCh
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, DEVICE_INT_CONFIG(PCH_DEVFN_PCIE6, int_B, PCIE_6_IRQ),
PCI_FUNC(PCH_DEVFN_PCIE6), int_B, PCIE_6_IRQ),
/* /*
* PCI Express Port 7, INT is default, * PCI Express Port 7, INT is default,
* programmed in PciCfgSpace + FCh * programmed in PciCfgSpace + FCh
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, DEVICE_INT_CONFIG(PCH_DEVFN_PCIE7, int_C, PCIE_7_IRQ),
PCI_FUNC(PCH_DEVFN_PCIE7), int_C, PCIE_7_IRQ),
/* /*
* PCI Express Port 8, INT is default, * PCI Express Port 8, INT is default,
* programmed in PciCfgSpace + FCh * programmed in PciCfgSpace + FCh
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, DEVICE_INT_CONFIG(PCH_DEVFN_PCIE8, int_D, PCIE_8_IRQ),
PCI_FUNC(PCH_DEVFN_PCIE8), int_D, PCIE_8_IRQ),
/* /*
* SerialIo UART Controller #2, INTA is default, * SerialIo UART Controller #2, INTA is default,
* programmed in PCR[SERIALIO] + PCICFGCTRL[9] * programmed in PCR[SERIALIO] + PCICFGCTRL[9]
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, DEVICE_INT_CONFIG(PCH_DEVFN_UART2, int_A, LPSS_UART2_IRQ),
PCI_FUNC(PCH_DEVFN_UART2), int_A, LPSS_UART2_IRQ),
/* /*
* SerialIo UART Controller #5, INTA is default, * SerialIo UART Controller #5, INTA is default,
* programmed in PCR[SERIALIO] + PCICFGCTRL[6] * programmed in PCR[SERIALIO] + PCICFGCTRL[6]
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, DEVICE_INT_CONFIG(PCH_DEVFN_I2C5, int_B, LPSS_I2C5_IRQ),
PCI_FUNC(PCH_DEVFN_I2C5), int_B, LPSS_I2C5_IRQ),
/* /*
* SerialIo UART Controller #4, INTA is default, * SerialIo UART Controller #4, INTA is default,
* programmed in PCR[SERIALIO] + PCICFGCTRL[5] * programmed in PCR[SERIALIO] + PCICFGCTRL[5]
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, DEVICE_INT_CONFIG(PCH_DEVFN_I2C4, int_C, LPSS_I2C4_IRQ),
PCI_FUNC(PCH_DEVFN_I2C4), int_C, LPSS_I2C4_IRQ),
/* /*
* SATA Controller, INTA is default, * SATA Controller, INTA is default,
* programmed in PciCfgSpace + 3Dh * programmed in PciCfgSpace + 3Dh
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_SATA, DEVICE_INT_CONFIG(PCH_DEVFN_SATA, int_A, SATA_IRQ),
PCI_FUNC(PCH_DEVFN_SATA), int_A, SATA_IRQ),
/* CSME: HECI #1 */ /* CSME: HECI #1 */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, DEVICE_INT_CONFIG(PCH_DEVFN_CSE, int_A, HECI_1_IRQ),
PCI_FUNC(PCH_DEVFN_CSE), int_A, HECI_1_IRQ),
/* CSME: HECI #2 */ /* CSME: HECI #2 */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, DEVICE_INT_CONFIG(PCH_DEVFN_CSE_2, int_B, HECI_2_IRQ),
PCI_FUNC(PCH_DEVFN_CSE_2), int_B, HECI_2_IRQ),
/* CSME: IDE-Redirection (IDE-R) */ /* CSME: IDE-Redirection (IDE-R) */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, DEVICE_INT_CONFIG(PCH_DEVFN_CSE_IDER, int_C, IDER_IRQ),
PCI_FUNC(PCH_DEVFN_CSE_IDER), int_C, IDER_IRQ),
/* CSME: Keyboard and Text (KT) Redirection */ /* CSME: Keyboard and Text (KT) Redirection */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, DEVICE_INT_CONFIG(PCH_DEVFN_CSE_KT, int_D, KT_IRQ),
PCI_FUNC(PCH_DEVFN_CSE_KT), int_D, KT_IRQ),
/* CSME: HECI #3 */ /* CSME: HECI #3 */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, DEVICE_INT_CONFIG(PCH_DEVFN_CSE_3, int_A, HECI_3_IRQ),
PCI_FUNC(PCH_DEVFN_CSE_3), int_A, HECI_3_IRQ),
/* /*
* SerialIo I2C Controller #0, INTA is default, * SerialIo I2C Controller #0, INTA is default,
* programmed in PCR[SERIALIO] + PCICFGCTRL[1] * programmed in PCR[SERIALIO] + PCICFGCTRL[1]
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, DEVICE_INT_CONFIG(PCH_DEVFN_I2C0, int_A, LPSS_I2C0_IRQ),
PCI_FUNC(PCH_DEVFN_I2C0), int_A, LPSS_I2C0_IRQ),
/* /*
* SerialIo I2C Controller #1, INTA is default, * SerialIo I2C Controller #1, INTA is default,
* programmed in PCR[SERIALIO] + PCICFGCTRL[2] * programmed in PCR[SERIALIO] + PCICFGCTRL[2]
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, DEVICE_INT_CONFIG(PCH_DEVFN_I2C1, int_B, LPSS_I2C1_IRQ),
PCI_FUNC(PCH_DEVFN_I2C1), int_B, LPSS_I2C1_IRQ),
/* /*
* SerialIo I2C Controller #2, INTA is default, * SerialIo I2C Controller #2, INTA is default,
* programmed in PCR[SERIALIO] + PCICFGCTRL[3] * programmed in PCR[SERIALIO] + PCICFGCTRL[3]
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, DEVICE_INT_CONFIG(PCH_DEVFN_I2C2, int_C, LPSS_I2C2_IRQ),
PCI_FUNC(PCH_DEVFN_I2C2), int_C, LPSS_I2C2_IRQ),
/* /*
* SerialIo I2C Controller #3, INTA is default, * SerialIo I2C Controller #3, INTA is default,
* programmed in PCR[SERIALIO] + PCICFGCTRL[4] * programmed in PCR[SERIALIO] + PCICFGCTRL[4]
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, DEVICE_INT_CONFIG(PCH_DEVFN_I2C3, int_D, LPSS_I2C3_IRQ),
PCI_FUNC(PCH_DEVFN_I2C3), int_D, LPSS_I2C3_IRQ),
/* /*
* USB 3.0 xHCI Controller, no default value, * USB 3.0 xHCI Controller, no default value,
* programmed in PciCfgSpace 3Dh * programmed in PciCfgSpace 3Dh
*/ */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, DEVICE_INT_CONFIG(PCH_DEVFN_XHCI, int_A, XHCI_IRQ),
PCI_FUNC(PCH_DEVFN_XHCI), int_A, XHCI_IRQ),
/* USB Device Controller (OTG) */ /* USB Device Controller (OTG) */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, DEVICE_INT_CONFIG(PCH_DEVFN_USBOTG, int_B, OTG_IRQ),
PCI_FUNC(PCH_DEVFN_USBOTG), int_B, OTG_IRQ),
/* Thermal Subsystem */ /* Thermal Subsystem */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, DEVICE_INT_CONFIG(PCH_DEVFN_THERMAL, int_C, THERMAL_IRQ),
PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THERMAL_IRQ),
/* Camera IO Host Controller */ /* Camera IO Host Controller */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, DEVICE_INT_CONFIG(PCH_DEVFN_CIO, int_A, CIO_INTA_IRQ),
PCI_FUNC(PCH_DEVFN_CIO), int_A, CIO_INTA_IRQ),
/* Integrated Sensor Hub */ /* Integrated Sensor Hub */
DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH, DEVICE_INT_CONFIG(PCH_DEVFN_ISH, int_A, ISH_IRQ)
PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ)
}; };
void soc_irq_settings(FSP_SIL_UPD *params) void soc_irq_settings(FSP_SIL_UPD *params)