mb/amd: Drop unneeded empty lines
Change-Id: Ib82689150689716bc9afdf8d4527a1dcd5deae56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes HAOUAS
Patrick Georgi
parent
d429c1a842
commit
85c681e279
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@ -10,7 +10,6 @@ Name(PR0, Package(){
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Package(){0x0001FFFF, 0, INTB, 0 },
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Package(){0x0001FFFF, 1, INTC, 0 },
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/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
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Package(){0x0002FFFF, 0, INTC, 0 },
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Package(){0x0002FFFF, 1, INTD, 0 },
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@ -70,7 +69,6 @@ Name(APR0, Package(){
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Package(){0x0011FFFF, 0, 0, 19 },
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})
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/* GPP 0 */
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Name(PS4, Package(){
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Package(){0x0000FFFF, 0, INTA, 0 },
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@ -1,6 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <AGESA.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <PlatformMemoryConfiguration.h>
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@ -30,7 +30,6 @@ Scope(\_GPE) { /* Start Scope GPE */
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/* DBGO("\\_GPE\\_L10\n") */
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}
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/* ExtEvent1 SCI event */
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Method(_L11) {
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/* DBGO("\\_GPE\\_L11\n") */
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@ -58,7 +58,6 @@ Device(PMRY)
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} /* end of PSLA */
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} /* end of PMRY */
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Device(SEDY)
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{
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Name(_ADR, 1) /* IDE Scondary Channel */
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@ -31,7 +31,6 @@ static void init_gpios(void)
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gpio_100_write8(0x32, 0x48);
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}
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/**********************************************
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* Enable the dedicated functions of the board.
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**********************************************/
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@ -1,6 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _PLATFORM_CFG_H_
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#define _PLATFORM_CFG_H_
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@ -109,7 +108,6 @@
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*/
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#define SATA_PORT_MULT_CAP_RESERVED 1
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/**
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* @def AZALIA_AUTO
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* @brief Detect Azalia controller automatically.
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@ -10,7 +10,6 @@ Name(PR0, Package(){
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Package(){0x0001FFFF, 0, INTB, 0 },
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Package(){0x0001FFFF, 1, INTC, 0 },
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/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
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Package(){0x0002FFFF, 0, INTC, 0 },
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Package(){0x0002FFFF, 1, INTD, 0 },
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@ -58,7 +57,6 @@ Name(APR0, Package(){
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Package(){0x0002FFFF, 2, 0, 26 },
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Package(){0x0002FFFF, 3, 0, 27 },
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/* SB devices in APIC mode */
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/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
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Package(){0x0014FFFF, 0, 0, 16 },
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@ -10,7 +10,6 @@ Name(PR0, Package(){
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Package(){0x0001FFFF, 0, INTB, 0 },
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Package(){0x0001FFFF, 1, INTC, 0 },
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/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
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Package(){0x0002FFFF, 0, INTC, 0 },
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Package(){0x0002FFFF, 1, INTD, 0 },
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@ -95,7 +95,6 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
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};
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static const PCIe_DDI_DESCRIPTOR DdiList[] = {
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/* DP0 */
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{
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@ -5,7 +5,6 @@
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#include <northbridge/amd/agesa/state_machine.h>
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/*
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* Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
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*
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@ -35,7 +35,6 @@ Scope(\_GPE) { /* Start Scope GPE */
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/* DBGO("\\_GPE\\_L10\n") */
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}
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/* ExtEvent1 SCI event */
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Method(_L11) {
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/* DBGO("\\_GPE\\_L11\n") */
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@ -1,11 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <AGESA.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <PlatformMemoryConfiguration.h>
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static const PCIe_PORT_DESCRIPTOR PortList[] = {
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// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
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{
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@ -30,7 +30,6 @@ Scope(\_GPE) { /* Start Scope GPE */
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/* DBGO("\\_GPE\\_L10\n") */
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}
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/* ExtEvent1 SCI event */
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Method(_L11) {
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/* DBGO("\\_GPE\\_L11\n") */
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@ -41,7 +41,6 @@ Scope(\_SB) {
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/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
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/* SB devices */
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/* Bus 0, Dev 17 - SATA controller */
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Package(){0x0011FFFF, 0, INTD, 0 },
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@ -58,7 +58,6 @@ Device(PMRY)
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} /* end of PSLA */
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} /* end of PMRY */
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Device(SEDY)
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{
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Name(_ADR, 1) /* IDE Scondary Channel */
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@ -1,6 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _PLATFORM_CFG_H_
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#define _PLATFORM_CFG_H_
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@ -109,7 +108,6 @@
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*/
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#define SATA_PORT_MULT_CAP_RESERVED 1
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/**
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* @def AZALIA_AUTO
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* @brief Detect Azalia controller automatically.
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@ -1,6 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <AGESA.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <PlatformMemoryConfiguration.h>
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@ -30,7 +30,6 @@ Scope(\_GPE) { /* Start Scope GPE */
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/* DBGO("\\_GPE\\_L10\n") */
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}
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/* ExtEvent1 SCI event */
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Method(_L11) {
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/* DBGO("\\_GPE\\_L11\n") */
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@ -58,7 +58,6 @@ Device(PMRY)
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} /* end of PSLA */
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} /* end of PMRY */
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Device(SEDY)
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{
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Name(_ADR, 1) /* IDE Scondary Channel */
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@ -1,6 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _PLATFORM_CFG_H_
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#define _PLATFORM_CFG_H_
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@ -109,7 +108,6 @@
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*/
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#define SATA_PORT_MULT_CAP_RESERVED 1
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/**
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* @def AZALIA_AUTO
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* @brief Detect Azalia controller automatically.
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@ -154,7 +154,6 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
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}
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}
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void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
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{
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FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
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@ -5,7 +5,6 @@
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#include <northbridge/amd/agesa/state_machine.h>
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/*
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* Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
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*
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@ -35,7 +35,6 @@ Scope(\_GPE) { /* Start Scope GPE */
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/* DBGO("\\_GPE\\_L10\n") */
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}
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/* ExtEvent1 SCI event */
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Method(_L11) {
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/* DBGO("\\_GPE\\_L11\n") */
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@ -30,7 +30,6 @@ Scope(\_GPE) { /* Start Scope GPE */
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/* DBGO("\\_GPE\\_L10\n") */
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}
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/* ExtEvent1 SCI event */
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Method(_L11) {
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/* DBGO("\\_GPE\\_L11\n") */
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@ -58,7 +58,6 @@ Device(PMRY)
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} /* end of PSLA */
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} /* end of PMRY */
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Device(SEDY)
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{
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Name(_ADR, 1) /* IDE Scondary Channel */
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@ -1,6 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _PLATFORM_CFG_H_
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#define _PLATFORM_CFG_H_
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@ -109,7 +108,6 @@
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*/
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#define SATA_PORT_MULT_CAP_RESERVED 1
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/**
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* @def AZALIA_AUTO
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* @brief Detect Azalia controller automatically.
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