soc/intel/alderlake/romstage: Refactor soc_memory_init_params function
This patch create separate helper functions to fill-in required FSP-M UPDs as per IP initialization categories. This would help to increase the code readability and in future meaningful addition of FSP-M UPDs is possible rather adding UPDs randomly. TEST=FSP-M UPD dump shows no change without and with this code change. Change-Id: I5f23292fd1bd44d0cd55fbefd490b090ccd48365 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55225 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik
Werner Zeh
parent
89a5f0f586
commit
85c9dda1c4
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@ -64,7 +64,34 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_typ
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}
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}
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static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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static void fill_fspm_pcie_rp_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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/* Disable all PCIe clock sources by default. And set RP irrelevant clock. */
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unsigned int i;
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for (i = 0; i < CONFIG_MAX_PCIE_CLOCK_SRC; i++) {
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if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING)
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m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING;
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else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN)
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m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN;
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else
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m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED;
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m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED;
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}
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/* Configure PCH PCIE ports */
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m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table());
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pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCH_PCIE_RP, config->pch_pcie_rp,
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CONFIG_MAX_PCH_ROOT_PORTS);
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/* Configure CPU PCIE ports */
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m_cfg->CpuPcieRpEnableMask = pcie_rp_enable_mask(get_cpu_pcie_rp_table());
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pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, CPU_PCIE_RP, config->cpu_pcie_rp,
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CONFIG_MAX_CPU_ROOT_PORTS);
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}
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static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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unsigned int i;
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@ -104,11 +131,18 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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*ddi_port_upds[i].hpd = 0;
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}
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}
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m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
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}
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static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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m_cfg->SaGv = config->SaGv;
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m_cfg->RMT = config->RMT;
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}
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static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
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/* CpuRatio Settings */
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if (config->cpu_ratio_override)
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m_cfg->CpuRatio = config->cpu_ratio_override;
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@ -118,9 +152,21 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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m_cfg->PrmrrSize = get_valid_prmrr_size();
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m_cfg->EnableC6Dram = config->enable_c6dram;
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/* Enable Hyper Threading */
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m_cfg->HyperThreading = 1;
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}
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static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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/* Disable BIOS Guard */
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m_cfg->BiosGuard = 0;
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m_cfg->TmeEnable = CONFIG(INTEL_TME);
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}
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static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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/* UART Debug Log */
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m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
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DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO;
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@ -128,23 +174,45 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8;
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m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit;
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m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
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}
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static void fill_fspm_ipu_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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/* Image clock: disable all clocks for bypassing FSP pin mux */
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memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn));
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/* IPU */
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m_cfg->SaIpuEnable = is_devfn_enabled(SA_DEVFN_IPU);
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}
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/* Enable Hyper Threading */
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m_cfg->HyperThreading = 1;
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static void fill_fspm_smbus_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS);
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}
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static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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/* Disable Lock PCU Thermal Management registers */
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m_cfg->LockPTMregs = 0;
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/* Enable SMBus controller */
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m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS);
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/* Set debug probe type */
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m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT;
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/* Skip CPU replacement check */
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m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck;
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/* Skip GPIO configuration from FSP */
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m_cfg->GpioOverride = 0x1;
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}
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static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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/* Audio: HDAUDIO_LINK_MODE I2S/SNDW */
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m_cfg->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA);
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m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
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m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode;
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m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency;
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m_cfg->PchHdaIDispCodecDisconnect = !config->PchHdaIDispCodecEnable;
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/*
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* All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to
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* configure GPIO pads for audio. Mainboard is expected to perform all GPIO
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@ -155,34 +223,17 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
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memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable));
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memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
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m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode;
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m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency;
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m_cfg->PchHdaIDispCodecDisconnect = !config->PchHdaIDispCodecEnable;
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}
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/* Disable all PCIe clock sources by default. And set RP irrelevant clock. */
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for (i = 0; i < CONFIG_MAX_PCIE_CLOCK_SRC; i++) {
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if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING)
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m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING;
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else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN)
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m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN;
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else
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m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED;
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m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED;
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}
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/* PCIE ports */
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m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table());
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pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCH_PCIE_RP, config->pch_pcie_rp,
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CONFIG_MAX_PCH_ROOT_PORTS);
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/* CPU PCIE ports */
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m_cfg->CpuPcieRpEnableMask = pcie_rp_enable_mask(get_cpu_pcie_rp_table());
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pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, CPU_PCIE_RP, config->cpu_pcie_rp,
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CONFIG_MAX_CPU_ROOT_PORTS);
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/* ISH */
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static void fill_fspm_ish_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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m_cfg->PchIshEnable = is_devfn_enabled(PCH_DEVFN_ISH);
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}
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static void fill_fspm_tcss_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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/* Tcss USB */
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m_cfg->TcssXhciEn = is_devfn_enabled(SA_DEVFN_TCSS_XHCI);
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m_cfg->TcssXdciEn = is_devfn_enabled(SA_DEVFN_TCSS_XDCI);
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@ -190,17 +241,20 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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/* TCSS DMA */
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m_cfg->TcssDma0En = is_devfn_enabled(SA_DEVFN_TCSS_DMA0);
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m_cfg->TcssDma1En = is_devfn_enabled(SA_DEVFN_TCSS_DMA1);
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}
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/* USB4/TBT */
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static void fill_fspm_usb4_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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m_cfg->TcssItbtPcie0En = is_devfn_enabled(SA_DEVFN_TBT0);
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m_cfg->TcssItbtPcie1En = is_devfn_enabled(SA_DEVFN_TBT1);
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m_cfg->TcssItbtPcie2En = is_devfn_enabled(SA_DEVFN_TBT2);
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m_cfg->TcssItbtPcie3En = is_devfn_enabled(SA_DEVFN_TBT3);
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}
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/* IPU */
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m_cfg->SaIpuEnable = is_devfn_enabled(SA_DEVFN_IPU);
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/* VT-d config */
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static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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m_cfg->VtdBaseAddress[VTD_GFX] = GFXVT_BASE_ADDRESS;
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m_cfg->VtdBaseAddress[VTD_IPU] = IPUVT_BASE_ADDRESS;
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m_cfg->VtdBaseAddress[VTD_VTVCO] = VTVC0_BASE_ADDRESS;
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@ -242,13 +296,13 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
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m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
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/* Skip CPU replacement check */
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m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck;
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}
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m_cfg->TmeEnable = CONFIG(INTEL_TME);
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/* Skip GPIO configuration from FSP */
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m_cfg->GpioOverride = 0x1;
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static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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/* Set debug probe type */
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m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT;
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/* CrashLog config */
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if (CONFIG(SOC_INTEL_CRASHLOG)) {
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@ -257,6 +311,32 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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}
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}
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static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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const void (*fill_fspm_params[])(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_alderlake_config *config) = {
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fill_fspm_igd_params,
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fill_fspm_mrc_params,
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fill_fspm_cpu_params,
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fill_fspm_security_params,
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fill_fspm_uart_params,
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fill_fspm_ipu_params,
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fill_fspm_smbus_params,
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fill_fspm_misc_params,
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fill_fspm_audio_params,
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fill_fspm_pcie_rp_params,
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fill_fspm_ish_params,
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fill_fspm_tcss_params,
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fill_fspm_usb4_params,
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fill_fspm_vtd_params,
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fill_fspm_trace_params,
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};
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for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++)
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fill_fspm_params[i](m_cfg, config);
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}
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void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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{
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const struct soc_intel_alderlake_config *config;
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