mb/hp: Add HP EliteBook Folio 9480m
The code is based on autoport, with necessary modifications. This laptop uses SMSC MEC1322 embedded controller, but the EC interface is the same as the EliteBook laptops of previous generations that use KBC1126 EC. So it still uses ec/hp/kbc1126, but does not need EC firmware inserted into CBFS. We also need to leave the end of the OEM flash content untouched, so the default ROM size is set to 12MiB instead of 16MiB, and we need to modify the IFD when flashing. Thanks to persmule for providing the laptop and pointing out how to program the system flash chip of it. Change-Id: I2328c43cbb1f488aa1d0ddd9116814d971e5d8ae Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Iru Cai
Patrick Georgi
parent
43cc3c0273
commit
85d0e7611a
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# HP EliteBook Folio 9480m
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This page is about the notebook [HP EliteBook Folio 9480m].
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## Release status
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HP EliteBook Folio 9480m was released in 2014 and is now end of life.
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It can be bought from a secondhand market like Taobao or eBay.
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## Required proprietary blobs
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The following blobs are required to operate the hardware:
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1. EC firmware
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2. Intel ME firmware
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3. mrc.bin
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HP EliteBook Folio 9480m uses SMSC MEC1322 as its embedded controller.
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The EC firmware is stored in the flash chip, but we don't need to touch it
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or use it in the coreboot build process.
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Intel ME firmware is in the flash chip. It is not needed when building coreboot.
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The Haswell memory reference code binary is needed when building coreboot.
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Please see [mrc.bin](../../northbridge/intel/haswell/mrc.bin).
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## Programming
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Before flashing, remove the battery and the hard drive cover according to the
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[Maintenance and Service Guide] of this laptop.
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HP EliteBook Folio 9480m has two flash chips, a 16MiB system flash, and a 2MiB
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private flash. To install coreboot, we need to program both flash chips.
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Read [HP Sure Start] for detailed information.
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To access the system flash, we need to connect the AC adapter to the machine,
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then clip on the flash chip with an SOIC-8 clip. An [STM32-based flash programmer]
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made with an STM32 development board is tested to work.
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To access the private flash chip, we can use a ch341a based flash programmer and
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flash the chip with the AC adapter disconnected.
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Before flashing coreboot, we need to do the following:
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1. Erase the private flash to disable the IFD protection
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2. Modify the IFD to shrink the BIOS region, so that we'll not use or override
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the protected bootblock and PEI region, as well as the EC firmware
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To erase the private flash chip, attach it with the flash programmer via the SOIC-8 clip,
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then run:
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flashrom -p <programmer> --erase
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To modify the IFD, we need a new flash layout. The flash layout of the OEM firmware is:
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00000000:00000fff fd
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00001000:00002fff gbe
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00003000:005fffff me
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00600000:00ffffff bios
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The default coreboot configuration sets the flash chip size to 12MiB, so set the end of the
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BIOS region to 0xbfffff in the new layout. The modified IFD is as follows (Platform Data
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region pd is the region protected by HP Sure Start):
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00000000:00000fff fd
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00001000:00002fff gbe
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00003000:005fffff me
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00600000:00bfffff bios
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00eb5000:00ffffff pd
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Write the above layout in a file, and use ifdtool to modify the IFD of a flash image.
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Suppose the above layout file is ``layout.txt`` and the origin content of the system flash
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is in ``factory-sys.rom``, run:
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ifdtool -n layout.txt factory-sys.rom
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Then a flash image with a new IFD will be in ``factory-sys.rom.new``.
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Flash the IFD of the system flash:
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flashrom -p <programmer> --ifd -i fd -w factory-sys.rom.new
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Then flash the coreboot image:
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# first extend the 12M coreboot.rom to 16M
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fallocate -l 16M build/coreboot.rom
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flashrom -p <programmer> --ifd -i bios -w build/coreboot.rom
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After coreboot is installed, the coreboot firmware can be updated with internal flashing:
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flashrom -p internal --ifd -i bios --noverify-all -w build/coreboot.rom
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## Debugging
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The board can be debugged with EHCI debug. The EHCI debug port is the USB port on the left.
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## Test status
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### Known issues
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- GRUB payload freezes just like previous EliteBook laptops
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- Sometimes the PCIe WLAN module can not be found in the OS after booting to the system
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- Sometimes all the USB devices can not be found in the OS after S3 resume
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### Untested
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- Fingerprint reader
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- Smart Card reader
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### Working
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- i5-4310U CPU with 4G+4G memory
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- SATA and M.2 SATA disk
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- Ethernet
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- WLAN
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- WWAN
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- SD card reader
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- USB
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- Keyboard and touchpad
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- DisplayPort
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- VGA
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- Dock
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- Audio output from speaker and headphone jack
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- Webcam
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- TPM
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- EC ACPI
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- S3 resume
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- Arch Linux with Linux 5.8.9
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- Memory initialization with mrc.bin version 1.6.1 Build 2
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- Graphics initialization with libgfxinit
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- Payload: SeaBIOS, Tianocore
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- EC firmware
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- KBC Revision 92.15 from OEM firmware version 01.33
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- KBC Revision 92.17 from OEM firmware version 01.50
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- Internal flashing under coreboot
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## Technology
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```eval_rst
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+------------------+-----------------------------+
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| CPU | Intel Haswell-ULT |
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+------------------+-----------------------------+
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| PCH | Intel Lynx Point Low Power |
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+------------------+-----------------------------+
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| EC | SMSC MEC1322 |
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+------------------+-----------------------------+
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| Coprocessor | Intel Management Engine |
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+------------------+-----------------------------+
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```
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[HP EliteBook Folio 9480m]: https://support.hp.com/us-en/product/hp-elitebook-folio-9480m-notebook-pc/7089926
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[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c05228980
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[STM32-based flash programmer]: https://github.com/dword1511/stm32-vserprog
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[HP Sure Start]: hp_sure_start.md
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Binary file not shown.
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After Width: | Height: | Size: 39 KiB |
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@ -64,6 +64,7 @@ The boards in this section are not real mainboards, but emulators.
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- [HP Sure Start](hp/hp_sure_start.md)
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- [EliteBook 2560p](hp/2560p.md)
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- [EliteBook 8760w](hp/8760w.md)
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- [EliteBook Folio 9480m](hp/folio_9480m.md)
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## Intel
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if BOARD_HP_FOLIO_9480M
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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# The board has a 16MB flash, but the end of the flash needs
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# to be reserved, so we use 12MB as default
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select BOARD_ROMSIZE_KB_12288
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select EC_HP_KBC1126
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_GMA_HAVE_VBT
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select INTEL_LYNXPOINT_LP
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select MAINBOARD_HAS_LIBGFXINIT
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM1
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select MAINBOARD_USES_IFD_GBE_REGION
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select NORTHBRIDGE_INTEL_HASWELL
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select SERIRQ_CONTINUOUS_MODE
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select SOUTHBRIDGE_INTEL_LYNXPOINT
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select SYSTEM_TYPE_LAPTOP
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config MAINBOARD_DIR
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string
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default "hp/folio_9480m"
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config MAINBOARD_PART_NUMBER
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string
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default "HP EliteBook Folio 9480m"
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config VGA_BIOS_FILE
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string
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default "pci8086,0a16.rom"
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config VGA_BIOS_ID
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string
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default "8086,0a16"
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config USBDEBUG_HCD_INDEX
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int
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default 1
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config EC_HP_KBC1126_ECFW_IN_CBFS
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bool
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default n
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config EC_HP_KBC1126_GPE
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hex
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default 0x6
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endif
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config BOARD_HP_FOLIO_9480M
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bool "EliteBook Folio 9480m"
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romstage-y += gpio.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <ec/hp/kbc1126/acpi/ec.asl>
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/* SPDX-License-Identifier: GPL-2.0-only */
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Method(_WAK,1)
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{
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\_SB.PCI0.LPCB.EC0.ACPI = 1
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\_SB.PCI0.LPCB.EC0.SLPT = 0
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Return(Package(){0,0})
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}
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Method(_PTS,1)
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{
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\_SB.PCI0.LPCB.EC0.SLPT = Arg0
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <drivers/pc80/pc/ps2_controller.asl>
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi_gnvs.h>
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#include <southbridge/intel/lynxpoint/nvs.h>
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void acpi_create_gnvs(struct global_nvs *gnvs)
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{
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gnvs->lids = 1;
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/* Temperature at which OS will shutdown */
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gnvs->tcrt = 100;
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/* Temperature at which OS will throttle CPU */
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gnvs->tpsv = 90;
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}
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Category: laptop
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Board URL: https://support.hp.com/us-en/product/hp-elitebook-folio-9480m-notebook-pc/7089926
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ROM protocol: SPI
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ROM package: SOIC-8
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ROM socketed: n
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Flashrom support: y
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Release year: 2014
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Binary file not shown.
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chip northbridge/intel/haswell
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register "dq_pins_interleaved" = "true"
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register "ec_present" = "true"
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register "gfx" = "GMA_STATIC_DISPLAYS(0)"
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register "gpu_dp_b_hotplug" = "4"
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register "gpu_dp_c_hotplug" = "4"
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register "gpu_panel_power_backlight_off_delay" = "1"
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register "gpu_panel_power_backlight_on_delay" = "1"
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register "gpu_panel_power_cycle_delay" = "6"
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register "gpu_panel_power_down_delay" = "500"
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register "gpu_panel_power_up_delay" = "2000"
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register "gpu_pch_backlight_pwm_hz" = "200"
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register "usb_xhci_on_resume" = "true"
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device cpu_cluster 0 on
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chip cpu/intel/haswell
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register "c1_battery" = "2"
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register "c2_battery" = "3"
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register "c3_battery" = "9"
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register "c1_acpower" = "2"
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register "c2_acpower" = "3"
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register "c3_acpower" = "9"
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device lapic 0 on end
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device lapic 0xacac off end
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end
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end
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device domain 0x0 on
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subsystemid 0x103c 0x22da inherit
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device pci 00.0 on end # Host bridge
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device pci 02.0 on end # Internal graphics VGA controller
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device pci 03.0 on end # Mini-HD audio
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chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
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register "gen1_dec" = "0x007c0201"
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register "gen2_dec" = "0x000c0101"
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register "gen4_dec" = "0x000402e9"
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register "xhci_default" = "1"
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register "sata_ahci" = "1"
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register "sata_port1_gen3_dtle" = "0x6"
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# SATA(1), M.2(3)
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register "sata_port_map" = "0xa"
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device pci 13.0 off end # Intel Smart Sound DSP
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device pci 14.0 on end # xHCI Controller
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device pci 15.0 off end # Serial I/O DMA
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device pci 15.1 off end # I2C0
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device pci 15.2 off end # I2C1
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device pci 15.3 off end # GSPI0
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device pci 15.4 off end # GSPI1
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device pci 15.5 off end # UART0
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device pci 15.6 off end # UART1
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 17.0 off end # SDIO
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device pci 19.0 on end # Intel Gigabit Ethernet
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 on end # PCIe Port #2, Realtek Card Reader
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device pci 1c.2 off end # PCIe Port #3
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device pci 1c.3 on # PCIe Port #4, WLAN
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smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther"
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"M.2 2230" "SlotDataBusWidth1X"
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end
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1d.0 on end # USB2 EHCI #1
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device pci 1f.0 on # LPC bridge
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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# This laptop uses MEC1322, but it has the same interface
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# as the KBC1126 laptops
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chip ec/hp/kbc1126
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register "ec_data_port" = "0x62"
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register "ec_cmd_port" = "0x66"
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register "ec_ctrl_reg" = "0x81"
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register "ec_fan_ctrl_value" = "0x6b"
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device pnp ff.1 off end
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end
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end
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device pci 1f.2 on end # SATA Controller (AHCI)
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device pci 1f.3 on end # SMBus
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device pci 1f.6 off end # Thermal
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end
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end
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end
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20141018 /* OEM revision */
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)
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{
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#include "acpi/platform.asl"
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#include <cpu/intel/common/acpi/cpu.asl>
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#include <southbridge/intel/common/acpi/platform.asl>
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/* global NVS and variables. */
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#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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Device (\_SB.PCI0)
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{
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#include <northbridge/intel/haswell/acpi/haswell.asl>
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#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
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#include <southbridge/intel/lynxpoint/acpi/pch.asl>
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}
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}
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-- SPDX-License-Identifier: GPL-2.0-or-later
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with HW.GFX.GMA;
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with HW.GFX.GMA.Display_Probing;
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use HW.GFX.GMA;
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use HW.GFX.GMA.Display_Probing;
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private package GMA.Mainboard is
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ports : constant Port_List :=
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(DP1, -- DP1/HDMI1: DisplayPorts on board and dock
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HDMI1,
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DP2, -- DP2: VGA ports on board and dock
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eDP,
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others => Disabled);
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end GMA.Mainboard;
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <southbridge/intel/lynxpoint/lp_gpio.h>
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const struct pch_lp_gpio_map mainboard_gpio_map[] = {
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[0] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
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[1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
|
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[2] = LP_GPIO_OUT_LOW,
|
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[3] = LP_GPIO_OUT_HIGH,
|
||||
[4] = LP_GPIO_OUT_HIGH,
|
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[5] = LP_GPIO_OUT_HIGH,
|
||||
[6] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
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[7] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
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[8] = LP_GPIO_OUT_HIGH,
|
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[9] = LP_GPIO_OUT_HIGH,
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[10] = LP_GPIO_OUT_HIGH,
|
||||
[11] = LP_GPIO_OUT_HIGH,
|
||||
[12] = LP_GPIO_NATIVE,
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[13] = LP_GPIO_OUT_HIGH,
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[14] = LP_GPIO_OUT_HIGH,
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[15] = LP_GPIO_OUT_HIGH,
|
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[16] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL,
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.route = GPIO_ROUTE_SMI },
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[17] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
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[18] = LP_GPIO_OUT_HIGH,
|
||||
[19] = LP_GPIO_NATIVE,
|
||||
[20] = LP_GPIO_NATIVE,
|
||||
[21] = LP_GPIO_NATIVE,
|
||||
[22] = LP_GPIO_OUT_HIGH,
|
||||
[23] = LP_GPIO_OUT_HIGH,
|
||||
[24] = LP_GPIO_OUT_HIGH,
|
||||
[25] = LP_GPIO_OUT_HIGH,
|
||||
[26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
|
||||
[27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
|
||||
[28] = LP_GPIO_OUT_HIGH,
|
||||
[29] = LP_GPIO_OUT_HIGH,
|
||||
[30] = LP_GPIO_NATIVE,
|
||||
[31] = LP_GPIO_NATIVE,
|
||||
[32] = LP_GPIO_NATIVE,
|
||||
[33] = LP_GPIO_NATIVE,
|
||||
[34] = LP_GPIO_OUT_HIGH,
|
||||
[35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
|
||||
[36] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL,
|
||||
.route = GPIO_ROUTE_SMI },
|
||||
[37] = LP_GPIO_NATIVE,
|
||||
[38] = LP_GPIO_NATIVE,
|
||||
[39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL,
|
||||
.route = GPIO_ROUTE_SMI },
|
||||
[40] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL,
|
||||
.route = GPIO_ROUTE_SMI },
|
||||
[41] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
|
||||
[42] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
|
||||
[43] = LP_GPIO_OUT_HIGH,
|
||||
[44] = LP_GPIO_OUT_LOW,
|
||||
[45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
|
||||
[46] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
|
||||
[47] = LP_GPIO_OUT_HIGH,
|
||||
[48] = LP_GPIO_OUT_LOW,
|
||||
[49] = LP_GPIO_OUT_HIGH,
|
||||
[50] = LP_GPIO_OUT_HIGH,
|
||||
[51] = LP_GPIO_OUT_HIGH,
|
||||
[52] = LP_GPIO_OUT_HIGH,
|
||||
[53] = LP_GPIO_OUT_HIGH,
|
||||
[54] = LP_GPIO_OUT_LOW,
|
||||
[55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL,
|
||||
.pirq = GPIO_PIRQ_APIC_ROUTE },
|
||||
[56] = LP_GPIO_OUT_HIGH,
|
||||
[57] = LP_GPIO_OUT_LOW,
|
||||
[58] = LP_GPIO_OUT_HIGH,
|
||||
[59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
|
||||
[60] = LP_GPIO_OUT_HIGH,
|
||||
[61] = LP_GPIO_OUT_LOW,
|
||||
[62] = LP_GPIO_NATIVE,
|
||||
[63] = LP_GPIO_NATIVE,
|
||||
[64] = LP_GPIO_OUT_HIGH,
|
||||
[65] = LP_GPIO_OUT_LOW,
|
||||
[66] = LP_GPIO_OUT_HIGH,
|
||||
[67] = LP_GPIO_OUT_HIGH,
|
||||
[68] = LP_GPIO_OUT_HIGH,
|
||||
[69] = LP_GPIO_OUT_HIGH,
|
||||
[70] = LP_GPIO_OUT_LOW,
|
||||
[71] = LP_GPIO_NATIVE,
|
||||
[72] = LP_GPIO_NATIVE,
|
||||
[73] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
|
||||
[74] = LP_GPIO_NATIVE,
|
||||
[75] = LP_GPIO_NATIVE,
|
||||
[76] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
|
||||
[77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
|
||||
[78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL,
|
||||
.route = GPIO_ROUTE_SMI },
|
||||
[79] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
|
||||
[80] = LP_GPIO_OUT_LOW,
|
||||
[81] = LP_GPIO_NATIVE,
|
||||
[82] = LP_GPIO_OUT_HIGH,
|
||||
[83] = LP_GPIO_OUT_HIGH,
|
||||
[84] = LP_GPIO_OUT_HIGH,
|
||||
[85] = LP_GPIO_OUT_HIGH,
|
||||
[86] = LP_GPIO_OUT_HIGH,
|
||||
[87] = LP_GPIO_OUT_HIGH,
|
||||
[88] = LP_GPIO_OUT_HIGH,
|
||||
[89] = LP_GPIO_OUT_HIGH,
|
||||
[90] = LP_GPIO_OUT_HIGH,
|
||||
[91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
|
||||
[92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
|
||||
[93] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
|
||||
[94] = LP_GPIO_OUT_HIGH,
|
||||
LP_GPIO_END
|
||||
};
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
0x10ec0280, /* Codec Vendor / Device ID: Realtek */
|
||||
0x103c22db, /* Subsystem ID */
|
||||
57, /* Number of 4 dword sets */
|
||||
AZALIA_SUBVENDOR(0, 0x103c22db),
|
||||
AZALIA_RESET(1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x0321101f),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x03a11020),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40738105),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
|
||||
/* The following is from the OEM firmware */
|
||||
0x02050007, 0x0204c200, 0x02050063, 0x02044800,
|
||||
0x02050066, 0x02040809, 0x02050015, 0x02048842,
|
||||
0x0205000f, 0x0204cccc, 0x02050010, 0x0204ccdd,
|
||||
0x02050065, 0x02042000, 0x0205001c, 0x0204c900,
|
||||
0x02050018, 0x02043788, 0x02050008, 0x02048210,
|
||||
0x02050068, 0x02043022, 0x02050006, 0x02040800,
|
||||
0x02050061, 0x02040403, 0x02050061, 0x02040403,
|
||||
0x0205005f, 0x02040800, 0x02050060, 0x02040800,
|
||||
0x0205002c, 0x02044002, 0x0205002e, 0x02041ec4,
|
||||
0x0205002f, 0x02040000, 0x02050033, 0x0204c5e8,
|
||||
0x02050034, 0x02041a98, 0x02050035, 0x0204f5ad,
|
||||
0x02050036, 0x0204cbd2, 0x02050037, 0x02041605,
|
||||
0x02050038, 0x0204f5ad, 0x02050039, 0x0204ea5f,
|
||||
0x0205003a, 0x02040b42, 0x0205003b, 0x0204fb54,
|
||||
0x0205003c, 0x0204fcd9, 0x0205003d, 0x02040000,
|
||||
0x02050030, 0x02041f5c, 0x02050031, 0x02040111,
|
||||
0x02050032, 0x02041f5f, 0x0205003e, 0x02041ea9,
|
||||
0x0205002f, 0x02040000, 0x02050042, 0x0204c66e,
|
||||
0x02050043, 0x02041a29, 0x02050035, 0x0204f5ad,
|
||||
0x02050044, 0x0204ccdd, 0x02050045, 0x02041549,
|
||||
0x02050038, 0x0204f5ad, 0x02050046, 0x0204ee79,
|
||||
0x02050047, 0x020409f4, 0x0205003b, 0x0204fb54,
|
||||
0x02050048, 0x0204fa4c, 0x0205003d, 0x02040000,
|
||||
0x0205003f, 0x02041f4d, 0x02050040, 0x02040129,
|
||||
0x02050041, 0x02041f51, 0x02050049, 0x02041f61,
|
||||
0x0205002f, 0x02040000, 0x0205004d, 0x0204c2f4,
|
||||
0x0205004e, 0x02041d2e, 0x02050035, 0x0204f5ad,
|
||||
0x0205004f, 0x0204c5e8, 0x02050050, 0x02041a98,
|
||||
0x02050038, 0x0204f5ad, 0x02050051, 0x0204d30e,
|
||||
0x02050052, 0x020413e6, 0x0205003b, 0x0204fb54,
|
||||
0x02050053, 0x02040b73, 0x0205003d, 0x02040000,
|
||||
0x0205004a, 0x02041faf, 0x0205004b, 0x0204008a,
|
||||
0x0205004c, 0x02041fb0, 0x02050054, 0x02041fb0,
|
||||
0x0205002f, 0x02040000, 0x02050058, 0x0204c17a,
|
||||
0x02050059, 0x02041e8f, 0x02050035, 0x0204f5ad,
|
||||
0x0205005a, 0x0204c2f4, 0x0205005b, 0x02041d2e,
|
||||
0x02050038, 0x0204f5ad, 0x0205005c, 0x0204c899,
|
||||
0x0205005d, 0x0204195b, 0x0205003b, 0x0204fb54,
|
||||
0x0205005e, 0x02041444, 0x0205003d, 0x02040000,
|
||||
0x02050055, 0x02041fd8, 0x02050056, 0x02040045,
|
||||
0x02050057, 0x02041fd8, 0x0205002c, 0x0204ffc2,
|
||||
0x02050026, 0x02042828, 0x02050029, 0x02040250,
|
||||
0x02050004, 0x0204c09e, 0x0205000e, 0x02045001,
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[0] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <northbridge/intel/haswell/haswell.h>
|
||||
#include <northbridge/intel/haswell/raminit.h>
|
||||
#include <southbridge/intel/lynxpoint/pch.h>
|
||||
|
||||
void mainboard_config_rcba(void)
|
||||
{
|
||||
RCBA16(D31IR) = DIR_ROUTE(PIRQF, PIRQD, PIRQC, PIRQA);
|
||||
RCBA16(D29IR) = DIR_ROUTE(PIRQB, PIRQD, PIRQA, PIRQC);
|
||||
RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA);
|
||||
RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD);
|
||||
RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD);
|
||||
RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQB, PIRQC, PIRQD);
|
||||
RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
|
||||
RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
|
||||
}
|
||||
|
||||
void mb_get_spd_map(uint8_t spd_map[4])
|
||||
{
|
||||
spd_map[0] = 0xa0;
|
||||
spd_map[2] = 0xa4;
|
||||
}
|
||||
|
||||
void mainboard_fill_pei_data(struct pei_data *pei_data)
|
||||
{
|
||||
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
|
||||
/* Length, Enable, OCn#, Location */
|
||||
{ 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* dock */
|
||||
{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* left, EHCI debug */
|
||||
{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* right */
|
||||
{ 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WLAN */
|
||||
{ 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* SmartCard */
|
||||
{ 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WWAN */
|
||||
{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* Webcam */
|
||||
{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
|
||||
};
|
||||
struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = {
|
||||
{ 1, USB_OC_PIN_SKIP }, /* dock */
|
||||
{ 1, USB_OC_PIN_SKIP }, /* left */
|
||||
{ 1, USB_OC_PIN_SKIP }, /* right */
|
||||
{ 0, USB_OC_PIN_SKIP },
|
||||
};
|
||||
memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports));
|
||||
memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports));
|
||||
}
|
||||
Loading…
Reference in New Issue